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Enhanced Rapidio interconnection device and equipment thereof

An enhanced, network technology, applied in the field of interconnection, can solve the problem of inability to complete the direct connection of chips, and achieve the effect of reducing the probability of system crash, improving system stability and increasing throughput.

Active Publication Date: 2020-12-29
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

RapidIO meets the requirements of high bandwidth and low latency, but its existing structure cannot complete the function of direct connection between chips. Therefore, this problem has brought great challenges to the development of embedded high-performance computing.

Method used

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  • Enhanced Rapidio interconnection device and equipment thereof
  • Enhanced Rapidio interconnection device and equipment thereof
  • Enhanced Rapidio interconnection device and equipment thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] Such as figure 1 As shown, the enhanced rapidio interconnection device (FT-Link for short) of this embodiment includes:

[0024] The network-AXI transfer bridge is used to perform dimension sequence operation and data bit width conversion on the sending and receiving data between the RapidIO soft core and the AXI host in the network;

[0025] RapidIO soft core, used to realize the conversion between AXI data packets and RapidIO data packets;

[0026] The network-AXI transition bridge is connected to the AXI host in the network through the AXI interface, and the RapidIO soft core is connected to the network-AXI through the write address channel, write data channel, write response channel, read address channel, and read data channel The bridge is connected, and the RapidIO soft core is connected with the AXI slave through the SERDES interface.

[0027] In this embodiment, the data bit width of the network side of the network-AXI transition bridge is 256 bits, and the da...

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Abstract

The invention discloses an enhanced Rapidio interconnection device and equipment thereof, and the device comprises a network-AXI switching bridge which is used for carrying out the dimension sequenceoperation and data bit width conversion of received and transmitted data between a RapidIO soft core and an AXI host in a network; the RapidIO soft core is used for realizing conversion of the AXI data packet and the RapidIO data packet; the network-AXI transfer bridge is connected with an AXI host in the network through an AXI interface, the RapidIO soft core is connected with the network AXI transfer bridge through a write address channel, a write data channel, a write response channel, a read address channel and a read data channel, and the RapidIO soft core is connected with the AXI slavethrough an SERDES interface. According to the method, the original RapidIO transmission mode is supported, and interconnection of multiple chips can be completed.

Description

technical field [0001] The invention relates to the internal interconnection technology of an embedded system, in particular to an enhanced rapidio interconnection device and equipment. Background technique [0002] The RapidIO protocol is the only one in the world developed to meet the unique needs of high-performance embedded systems. It has high speed, low latency and high reliability, and can meet the needs of high-speed data transmission in different scenarios. This research field has been highly concerned by the industry, and a series of research has been carried out. Domestic related research mainly focuses on the use of soft cores for secondary development and nuclear application research. The traditional method of using RapidIO is that programmers use RapidIO's built-in DMA (direct memory access) engine to transmit large batches of continuous data between the inside of the chip and the outside of the chip, which can effectively utilize the inherent high bandwidth an...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/40
CPCG06F13/1668G06F13/4013
Inventor 张洋毛李陈小文赵恒刘胜陈胜刚刘畅李晨
Owner NAT UNIV OF DEFENSE TECH
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