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Test structure and manufacturing method thereof

A technology for testing structures and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc. Effect

Pending Publication Date: 2020-12-29
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present disclosure is to provide a test structure and a manufacturing method thereof, so as to overcome at least to a certain extent the limitations and defects of related technologies that cause cracks in the dicing line caused by test circuit metal wires during wafer dicing, thereby destroying the wafer. grain area problem

Method used

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  • Test structure and manufacturing method thereof
  • Test structure and manufacturing method thereof
  • Test structure and manufacturing method thereof

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Embodiment Construction

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0043] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the description in the accompanying drawings directions for the example described above. It will be appreciated that if the illustrated device is turned over so...

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Abstract

The invention relates to a test structure and a manufacturing method thereof. The test structure comprises a substrate, a test circuit, a crack arrest groove and a sealing layer, wherein the substratecomprises a cutting area; a test circuit which is formed in the cutting area; crack arrest grooves which are formed in the cutting area, and the crack arrest grooves are distributed in the side partof the test circuit; and the sealing layer is formed on the surface of the substrate and covers the crack arrest groove so as to form a gas gap in the crack arrest groove. Through the crack arrest groove, a problem that when the wafer is cut along the cutting channel, the cutting channel cracks due to the influence of the metal layer in the test circuit, cutting stress is transmitted to the crystal grain area, and then the crystal grain area is possibly damaged is solved, and the yield and stability of products are improved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, in particular, to a test structure and a manufacturing method thereof. Background technique [0002] With the development and progress of technology, the application of integrated circuits is becoming more and more extensive. Wafers are one of the main materials of integrated circuits. During the production process of integrated circuits, wafers need to be cut to form multiple crystal grains. [0003] In order to facilitate cutting, a cutting area for cutting is usually set in the wafer. A detection circuit is set in the cutting area to test the performance of the components in the die. There are a large number of metal wires in the test circuit, and the metal wires are attached to the cutting area. surface. During the wafer dicing process, when the cutter touches the metal wire, it is easy to pull the wire and cause cracks in the cutting area, which may damage the grain area, re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/48
CPCH01L21/4814H01L23/544
Inventor 张志伟
Owner CHANGXIN MEMORY TECH INC