Method for realizing conversion from high-frame-frequency progressive image to standard-definition PAL interlaced image based on FPGA

Abstract

The invention discloses a method for converting a high-frame-frequency progressive image into a standard-definition PAL interlaced image based on an FPGA. The method comprises the steps of: taking a time sequence of a BT656 data frame as a reference, generating three control signals for controlling the ping-pong read-write operation of cache chips, carrying out the ping-pong control over the two cache chips, and carrying out the write operation and read operation, thereby achieving the conversion from the high-frame-frequency progressive image to the standard-definition PAL interlaced image. According to the method, the constraint on a relationship between periods of the BT656 data frame and an input image is relaxed, and only the period of the input image is required to be less than or equal to half of the period of the BT656 data frame, so that the stable display of a PAL standard-definition analog image is ensured, and hardware resources and cost are saved.

Description

technical field [0001] The invention belongs to the field of digital signal processing, and in particular relates to an FPGA-based method for converting a high frame rate progressive image into a standard-definition PAL interlaced image. Background technique [0002] In the real-time image processing platform, it is often necessary to output the input high frame rate progressive image to the chip ADV7393 through the cache chip and the parallel hardware interface defined by Itu-r bt.656 to realize interlaced PAL SD image display. The Itu-r bt.656 parallel hardware interface is used to transmit a 4:2:2 YCbCr digital video stream, hereinafter referred to as BT656. Since the BT656 data frame period is fixed at 40ms, if two cache chips are used, the input image period must match it, which is 20ms or 40ms, otherwise the output PAL image will shake up and down and cannot be displayed stably; if three cache chips are used , although the stable display of PAL images can be realized,...

AI Technical Summary

Problems solved by technology

Since the BT656 data frame period is fixed at 40ms, if two cache chips are used, the input image period must match it, which is 20ms or 40ms, otherwise the output PAL image will shake up and down and cannot be displayed stably; if three cache chips are used , although the stable display of PAL images can be achieved, and the requirements for the image cycle are not so strict, but in terms of hardware cost and circuit size, there is an additional cost of a cache chip

Especially for some generalized hardware platforms with only 2 cache chips, in the face of image input with different frame rates, the stable display of PAL images cannot be realized by using the original common control method

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