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Memory with stress circuitry for detecting defects

A technology of storage unit and access circuit, which is applied in static memory, digital memory information, information storage, etc., and can solve the problems of expensive integrated circuit testing table and increase the manufacturing cost of integrated circuit devices, etc.

Inactive Publication Date: 2003-09-24
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, such IC test benches are extremely expensive
The additional integrated circuit test station greatly increases the overall manufacturing cost of the integrated circuit device

Method used

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  • Memory with stress circuitry for detecting defects
  • Memory with stress circuitry for detecting defects
  • Memory with stress circuitry for detecting defects

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] figure 1 A static random access memory (SRAM) 20 of one embodiment is shown. SRAM 20 includes an access control circuit 24 , a set of sense amplifiers 30 - 32 and an array 22 of memory cells. Memory cell array 22 includes a set of memory cells 40-48. SRAM 20 also includes a set of pull-down transistors Q8-Q13.

[0033] Access control circuit 24 drives a set of word lines 60 - 62 of memory cell array 22 . Access control circuitry 24 drives word lines 60-62 to perform read and write operations on memory cells 40-48.

[0034] Each word line 60 - 62 corresponds to a row of memory cell array 22 . For example, word line 60 corresponds to the row of memory cell array 22 that contains memory cells 40-42. Likewise, word line 61 corresponds to the row of memory cells 22 containing memory cells 43-45, and word line 62 corresponds to the row containing memory cells 46-48.

[0035] Sense amplifiers 30-32 are connected to bit line sets 70-72 of memory cell array 22. As shown in...

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PUM

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Abstract

A memory circuit (20) with enhanced circuitry for detecting data retention defects in memory cells. The memory circuit (20) includes an array of memory cells (22) connected to the bit lines, an access circuit (24) connected to access the memory cells, and a discharge circuit connected to strengthen the memory cells.

Description

technical field [0001] This invention relates to the field of integrated circuit devices, and more particularly to random access memories with circuits having enhanced memory cells. Background technique [0002] A typical prior art static random access memory (SRAM) contains an array of SRAM cells. Each SRAM cell typically contains a set of 6 transistors. The six transistors in this typical SRAM are arranged as a pair of cross-coupled inverter circuits and a pair of pass gates. The pull-up transistor of the inverter circuit generally prevents leakage current in the SRAM cell from the discharge of the internal data storage node of the SRAM cell. [0003] Such SRAMs are typically implemented on integrated circuit dies according to the process technology used to fabricate semiconductor and metal interconnect structures on integrated circuit dies. Typically, semiconductor structures include diffusion regions and polysilicon structures for transistors in SRAMs. Metal intercon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C13/00G01R31/28G11C11/413G11C29/06G11C29/50
CPCG11C11/41G11C29/50G11C29/50016
Inventor E·罗森Y·米尔斯坦
Owner INTEL CORP