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FPGA (Field Programmable Gate Array) refreshing method suitable for satellite-borne XILINX V2

An on-board, pin-based technology, applied in the field of onboard XILINX V2 FPGA refresh, to extend trouble-free working time, avoid accumulation, and prolong life

Pending Publication Date: 2021-01-15
BEIJING RES INST OF TELEMETRY +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If a single event upset occurs that affects user applications, it can only be corrected by reconfiguring the FPGA

Method used

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  • FPGA (Field Programmable Gate Array) refreshing method suitable for satellite-borne XILINX V2
  • FPGA (Field Programmable Gate Array) refreshing method suitable for satellite-borne XILINX V2
  • FPGA (Field Programmable Gate Array) refreshing method suitable for satellite-borne XILINX V2

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0048] 1. Configure storage architecture

[0049]The most basic configuration unit in the V2 architecture is the frame. The configuration frame group consists of CLB, IOB, IOI, GCLK, BRAM, BRAMInterconnects columns. Columns are divided into three block types: CLB (including GLKC, CLB, IOB1&2), BRAM and BRAMInterconnects. The V2 configuration storage space architecture is as follows: figure 1 shown.

[0050] The V2 frame address starts from 0x00000000h (the starting address of the GCLK column in the middle of the device), and the frame address starts to increase until it reaches the leftmost IOB column, and then increases to the right. The frame address register consists of three parts, block address, main address and minor address. When an FDRI or FDRO command calls to configure a multiframe or read back a multiframe, the frame address register automatically increments the minor address, major address, and block address. Block address 00 covers all GCLK, IOB, IOI and CLB ...

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Abstract

The invention discloses an FPGA refreshing method suitable for satellite-borne XILINX V2. Single event upset of non-single event function interruption can be corrected through refreshing; single eventupset of single event function interruption can only be recovered by lowering the PROG pin and reconfiguring the FPGA. The refreshing function can avoid accumulation of a single event effect, prolongthe working time of the satellite-borne signal processing FPGA and improve the reliability of satellite-borne equipment. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not affect the function of the signal processing FPGA. The invention further provides a step of increasing the frame address during refreshing and a refreshing command based on the frame.

Description

technical field [0001] The invention relates to a refreshing method suitable for on-board XILINX V2 FPGA. Background technique [0002] When spaceborne electronic equipment is in orbit, the impact of cosmic high-energy rays on electronic equipment must be considered. A single event flip changes the logical state of a static storage element. The functionality of the FPGA depends on the data stored in the FPGA's million configuration registers. Single-event flips in configuration memory arrays can have significant effects on desired functionality. A single-event flip of configuration storage may or may not affect functionality. The single event flip effect can be eliminated by adopting triple-mode redundant design technology. [0003] The V2 series FPGA SelectMap interface realizes the most effective post-configuration control by reading or writing to the configuration storage array. Readback is a configuration read operation after configuration storage, and partial recon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/654G06F11/10
CPCG06F8/654G06F11/1004
Inventor 张秀宁刘斌李澎吴昊史江博陈子君
Owner BEIJING RES INST OF TELEMETRY