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Phase-locked loop (PLL) circuit and clock generator including a sub-sampling circuit

A phase-locked loop, sub-sampling technology, applied in the direction of electrical components, automatic power control, output stability, etc., can solve problems such as changing the loop bandwidth of the PLL circuit

Pending Publication Date: 2021-01-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Because the snubber circuit usually includes complementary metal-oxide-semiconductor (CMOS) transistors, the snubber circuit is susceptible to

Method used

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  • Phase-locked loop (PLL) circuit and clock generator including a sub-sampling circuit
  • Phase-locked loop (PLL) circuit and clock generator including a sub-sampling circuit
  • Phase-locked loop (PLL) circuit and clock generator including a sub-sampling circuit

Examples

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Embodiment Construction

[0025] Embodiments provide a phase-locked loop (PLL) circuit and a clock generator capable of adjusting the loop bandwidth of the clock generator or the PLL circuit to be constant or by tracking the loop bandwidth that varies according to changes in noise characteristics. Generate reliable clocks.

[0026] figure 1 is a block diagram showing a clock generator according to an embodiment.

[0027] refer to figure 1 , the clock generator 10 may include a phase-locked loop (PLL) circuit PLL_CKT, and the PLL circuit PLL_CKT may include an auxiliary PLL circuit 20 , a sub-sampling PLL circuit 30 , and a voltage-controlled oscillator (VCO) 40 . Hereinafter, the VCO 40 may be implemented in various configurations such as a ring oscillator or an inductor-capacitor (LC) oscillator.

[0028] The auxiliary PLL circuit 20 may receive an output clock (or oscillation signal) from the VCO 40 as feedback, and perform a primary phase lock operation. Hereinafter, the primary phase-locking op...

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Abstract

The present invention provides a phase-locked loop (PLL) circuit and clock generator including a sub-sampling circuit. The phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from Korean Patent Application No. 10-2019-0087095 filed with the Korean Intellectual Property Office on July 18, 2019, the entire disclosure of which is hereby incorporated by reference. technical field [0003] The present disclosure relates to a phase locked loop (PLL) circuit and a clock generator including a subsampling phase locked loop (PLL) circuit for locking the phase of a clock. Background technique [0004] A PLL circuit or a clock generator including a PLL circuit can generate a phase-locked clock signal. For example, a clock signal can be used to send data by a transmitter or to recover data by a receiver. In this case, the PLL circuit may include a loop PLL circuit, an inductor-capacitor (LC)-PLL circuit, or the like. [0005] Recently, a technique of improving noise characteristics by locking the phase of a clock by subsampling has been applied to a PLL...

Claims

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Application Information

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IPC IPC(8): H03L7/18
CPCH03L7/18H03L7/087H03L7/091H03L1/02H03L7/0891H03L7/093H03L7/099H03L7/107
Inventor 郑在洪郑相敦吴承贤李京珉
Owner SAMSUNG ELECTRONICS CO LTD
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