Low-power adder circuit
An adder, low-power technology, applied in the field of hardware circuits, can solve the problems of expensive, no advantage in computing throughput, and efficiently adjust the size of the adder circuit
Pending Publication Date: 2021-01-19
GOOGLE LLC
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Problems solved by technology
Adder circuits can be expensive to produce and integrate into existing computing circuits, and some adder circuits are not sized efficiently for some applications
These circuits can consume considerable area of a circuit die, but have no advantage in terms of computational throughput despite their large size
Oversized adder circuits for some computing applications can result in poor power consumption and utilization
Method used
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[0039] In one example implementation, hardware circuits can be used to implement a multilayer neural network and perform computations (eg, neural network computations) by processing inputs by each layer of the neural network. In particular, the individual layers of the neural network can each have a corresponding set of parameters. Each layer receives an input and processes the input in accordance with a parameter set for that layer to generate an output based on calculations performed using one or more adder circuits of the example computing unit. For example, the neural network layer can sum multiple inputs as part of computing a matrix multiplication of an input array with a parameter array or as part of computing a convolution between an input array and a parameter kernel array.
[0040] Typically, processing input through the layers of a neural network is done by performing mathematical operations such as multiplication and addition. The hardware circuitry can include a ...
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Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.
Description
technical field [0001] This specification relates to hardware circuits for performing mathematical calculations. Background technique [0002] The computing circuitry can include a number of adder circuits for summing numerical inputs such as integers and floating point numbers. Adder circuits can be expensive to produce and integrate into existing computing circuits, and some adder circuits are not efficiently sized for certain applications. These circuits can consume considerable area of a circuit die, but have no advantage in terms of computational throughput despite their large size. An oversized adder circuit for some computing applications may result in poor power consumption and utilization. [0003] Hardware circuits can be used to implement neural networks. A neural network with multiple layers can be used for computational inference by using computational circuitry including multiple adder circuits. Computational circuitry of a hardware circuit can also repre...
Claims
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IPC IPC(8): G06F7/485
CPCG06F7/485G06F7/50G06F17/10G06N3/063
Inventor 阿南德·苏雷什·卡纳拉维·纳拉亚纳斯瓦米
Owner GOOGLE LLC