A clock alignment system and method for prototype verification system

Abstract

An embodiment of the present disclosure provides a clock alignment system and method for a prototype verification system, the system includes a phase detection logic module and a plurality of FPGA chips, the FPGA chip includes a clock generator, and the clock generator includes A phase-locked loop circuit and a phase adjustment module, the phase detection logic module includes an exclusive OR logic circuit and an output phase controller. The system and method of the present invention can realize the phase alignment of multi-chip FPGA derived clocks, provide users with more flexible clock schemes, and reduce the burden on users to process clock trees.

Description

technical field [0001] The present disclosure relates to the technical field of signal acquisition and transmission, and in particular to a clock alignment system and method for a prototype verification system. Background technique [0002] In the verification stage of integrated circuits, FPGAs are generally selected for prototype verification. User designs are cut into multiple parts and placed on multiple FPGAs. In order to ensure that the cut designs can run normally, it is necessary to ensure that the clock phases of multiple FPGAs are consistent. , the general approach is to ensure that the clock buffers on the hardware to take paths of equal length to each FPGA, and physically guarantee the equal length of the phases. However, general users also use this clock to generate more derived clocks, including various frequency divisions. Although the phases of the main clock are completely consistent, when generating a frequency-divided clock from a high-frequency clock, the...

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Problems solved by technology

However, general users also use this clock to generate more derived clocks, including various frequency divisions. Although the phases of the main clock are completely consistent, when generating a frequency-divided clock from a high-frequency clock, the frequency of the frequency-divided clock phase may be misaligned

[0003] like figure 1 As shown, FPGA_clkdiv4 is the 4-divided clock of the input clock, which is aligned with the edge of the input clock, but the clocks of the three FPGAs in the figure are not aligned, which will affect the data communication between designs. It is necessary to synchronize the phases of these derived clocks to meet the design requirements.

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