Rapid control method for flash memory controller based on hardware
A flash memory controller and hardware implementation technology, applied in memory systems, instruments, memory address/allocation/relocation, etc., which can solve the problems of high CPU processing load and cumbersome command operations.
Pending Publication Date: 2021-02-05
BEIJING ZETTASTONE TECH CO LTD
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[0003] However, these technical solutions in the prior art are suitable for occasions where there are relatively few flash memory arrays. With the increase of flash memory particle channels, more and more flash memory controllers are required. In addition, with the popularity of TLC / QLC flash memory particles, the command The operation is becoming more and more cumbersome, and the CPU processing load is getting higher and higher
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[0024] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of illustration in order to fully convey the spirit of the present invention to those skilled in the art to which the present invention pertains. Therefore, the present invention is not limited to the embodiments disclosed herein.
[0025] Non-volatile solid-state storage is a storage device that uses flash memory (NANDFlash) as the medium, in which the flash memory controller is responsible for completing parallel operations on the flash memory array, including data Program / Read / Erase, etc. With the continuous improvement of IOPS and flash memory parallelism, the The requirements for the delay of issuing operation commands by the flash memory controller are getting higher and higher.
[0026] Those skilled in the art know that linknode is the smallest node unit for the flash memory controller...
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The invention provides a rapid control method for a flash memory controller based on hardware. The rapid control method comprises the following steps that an NVM controller receives a command from a host, and after the command passes through a command pre-analysis unit, data transmission commands are disassembled by the hardware; when the data transmission command is a write operation command, a cache space used for writing data is applied for, a linknode ID is applied for and a linknode command is generated, wherein the linknode command comprises the ID of the cache space; a CPU obtains the link IDs from a command parsing unit, and merges the plurality of link IDs to establish a link so as to merge the link IDs into an optask; the CPU pushes the optask to a command acceleration unit, andthe command acceleration unit generates opcmd and pushes the opcmd to a flash memory controller; when the data transmission command is a read operation command, data is read from the flash memory particles and writing the data into a data buffer; and meanwhile, the NVM controller is notified to take away the data.
Description
technical field [0001] The invention relates to the technical field of flash memory controllers, in particular to a hardware-based fast control method for flash memory controllers. Background technique [0002] At present, with the increase of solid-state storage capacity, NANDFLASH arrays are required to perform parallel operations to improve access speed. Among them, the flash memory controller implemented by hardware is mainly used to realize the interaction with the flash memory particle commands and data. The CPU generates commands in a specific format and sends them to the flash memory controller for execution. [0003] However, these technical solutions in the prior art are suitable for occasions where there are relatively few flash memory arrays. With the increase of flash memory particle channels, more and more flash memory controllers are required. In addition, with the popularity of TLC / QLC flash memory particles, the command The operation is also becoming more a...
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Login to View More IPC IPC(8): G06F12/02
CPCG06F12/0246
Inventor 向雄胡圣领
Owner BEIJING ZETTASTONE TECH CO LTD