Design method of on-chip photonic device based on appearance contour regulation and control

Abstract

The invention provides a design method of an on-chip photonic device based on appearance contour regulation and control. The design method comprises the steps of determining functions, a design targetand a design area of the device; discretizing the appearance contour of the device in the design area into a plurality of points; restoring the appearance profile curve of the device on the basis ofthe discrete points in the previous step by using an interpolation method, and replacing the original appearance profile curve; and performing iterative search on the discrete points by using a searchalgorithm, and changing the appearance contour in the design area until the device meets the design target. By adopting the technical scheme of the invention, the design method and the design dimension of the on-chip photonic device are expanded, the requirements of the on-chip photonic device on wider bandwidth, higher error tolerance and smaller size are met, the design goals of more functions,higher standards and smaller size are achieved, and the convergence rate is greatly improved.

Description

technical field [0001] The invention belongs to the technical field of on-chip photonic device design, and in particular relates to a design method of an on-chip photonic device based on appearance contour control. Background technique [0002] At present, it is a relatively mainstream design method to perform parametric discretization on the complete silicon structure in the set area, and then combine search algorithms to design on-chip photonic devices, but this method is only for optimal design in the set area, and for In pursuit of higher performance, the size of the discrete silicon structure is often relatively small, and the small size of the silicon structure often has a great impact on the bandwidth of the device and the error tolerance of the final fabrication. At the same time, for large-scale devices, the small-scale discrete silicon structure also means a larger parameter space, and the corresponding search algorithm cannot take into account the search efficienc...

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Problems solved by technology

[0002] At present, it is a relatively mainstream design method to perform parametric discretization on the complete silicon structure in the set area, and then combine search algorithms to design on-chip photonic devices, but this method is only for optimal design in the set area, and for In pursuit of higher performance, the size of the discrete silicon structure is often relatively small, and the small size of the silicon structure often has a great impact on the bandwidth of the device and the error tolerance of the final fabrication

At the same time, for large-scale devices, the small-scale discrete silicon structure also means a larger parameter space, and the corresponding search algorithm cannot take into account the search efficiency and the global optimal solution at the same time. In order to enable the optimization region to contain enough discrete silicon structures to meet our desired functions, the device structure cannot be too small

Therefore, the existing on-chip photonic device design methods limit the design dimension of the device on the one hand, and cannot meet the requirements of wider bandwidth, higher error tolerance and smaller size of on-chip photonic devices. It takes a lot of time to search for the best solution

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