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Resolver feedback signal frequency division method and system based on ad2s1210 resolver decoder chip

A AD2S1210, resolver decoding technology, applied in the direction of control system, general control system, vector control system, etc., can solve the problem of non-orthogonal pulse signal frequency division and other problems

Active Publication Date: 2022-06-17
SHENZHEN HPMONT TECH
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention provides a frequency division method of a resolver feedback signal based on the AD2S1210 resolver decoding chip to solve the technical problem in the prior art that the orthogonal pulse signal output by the AD2S1210 resolver decoding chip cannot be divided by any integer multiple.

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  • Resolver feedback signal frequency division method and system based on ad2s1210 resolver decoder chip
  • Resolver feedback signal frequency division method and system based on ad2s1210 resolver decoder chip
  • Resolver feedback signal frequency division method and system based on ad2s1210 resolver decoder chip

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Embodiment 1

[0050] Please refer to figure 1 , is a schematic diagram of the structure and connection of a resolver feedback signal frequency division system in an embodiment, including a motor 10 with a resolver, a resolver feedback signal frequency division system 20 , a main control unit 30 and a frequency division output terminal 40 . The resolver feedback signal frequency division system 20 is used for decoding the resolver signal. The resolver feedback signal frequency division system 20 includes an FPGA22 and an AD2S1210 resolver decoding chip 21. The main control unit and the FPGA22 write address and data pairs through serial communication. AD2S1210 resolver decoding chip 21 is configured. The AD2S1210 resolver decoding chip 21 generates EXC+ / EXC- signals and sends them to the motor 10 with the resolver, and receives the SIN / COS signal fed back by the motor 10 with the resolver. According to the configuration information sent by the main control unit 30, the AD2S1210 resolver deco...

Embodiment 2

[0055] Please refer to figure 2 , is a schematic flowchart of a method for dividing the frequency of a resolver feedback signal in another embodiment, and the method for dividing the frequency of a resolver feedback signal includes:

[0056] Step 100: Obtain a resolver feedback signal.

[0057] The resolver feedback signal is the A-phase pulse signal, B-phase pulse signal, NM-phase pulse signal and DIR direction signal output by the AD2S1210 resolver decoding chip according to a preset number of lines. Among them, the A-phase pulse signal and the B-phase pulse signal are mutually positive. The DIR direction signal is used to judge the following relationship between the A-phase pulse signal and the B-phase pulse signal. In one embodiment, the value of the preset number of lines is 16384.

[0058] Step 200, obtaining the frequency division coefficient sel.

[0059] The frequency division coefficient sel is the multiple of the frequency division of the resolver feedback signa...

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Abstract

A method for frequency division of a resolver feedback signal based on the AD2S1210 resolver decoder chip, comprising: first obtaining the A-phase pulse signal, the B-phase pulse signal and the NM-phase pulse signal output by the AD2S1210 resolver decoder chip according to a preset number of lines; Obtain the frequency division coefficient sel, and obtain the period value reset of the frequency division pulse count of the leading phase pulse signal according to the frequency division coefficient sel cnt and the period value half of the frequency division pulse count of the lagging phase pulse signal cnt . Then XOR the A-phase pulse signal and the B-phase pulse signal to obtain the pulse signal clk AB , according to the period value half cnt and period value reset cnt For pulse signal clk AB The rising or falling edge marks the edge information, and according to the pulse signal clk AB and edge information to obtain the frequency-divided outA pulse signal and outB pulse signal. Due to the pulse signal clk AB Rising edge or falling edge is marked with edge information to carry out frequency division to realize arbitrary integer frequency division processing of the orthogonal pulse signal output by AD2S1210 resolver decoding, which not only simplifies the frequency division process, but also is convenient and flexible.

Description

technical field [0001] The invention relates to the technical field of motor control, in particular to a resolver feedback signal frequency division method and system based on an AD2S1210 resolver decoding chip. Background technique [0002] A resolver is a precision angle, position and speed detection device. For a motor with a resolver, the resolver decoding system can analyze the position and speed information of the motor rotor from the analog signal output by the resolver with the angle change of the motor rotor. And provide it to the motor driver (inverter, servo driver, etc.) for the closed-loop control of the motor's own speed and position. At the same time, the resolver decoding system can also output the rotor position and speed information of the motor to the post-stage control in the form of quadrature pulses. system, so as to achieve multi-level control system linkage control. However, due to the different transmission ratios between different control systems, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02P23/14H02P21/18H02P6/17G05B19/042
CPCH02P23/14H02P21/18H02P6/17G05B19/0423G05B2219/25392
Inventor 马佳倚熊志伟张宁
Owner SHENZHEN HPMONT TECH
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