Sparse activation perception type neural network accelerator based on FPGA

Abstract

The invention discloses a sparse activation perception type neural network accelerator based on an FPGA. The sparse activation perception type neural network accelerator comprises a read command generator, a data distributor, Tm operation sub-channels, a multiply-accumulate array with the size of Tm*Tn, an addition tree group composed of Tn addition trees, a function module and an output cache. The data distributor distributes the data read by an off-chip memory to the operation sub-channels as few as possible. And the operation channel sends the weight and the non-zero activation to the multiply-accumulate array, and the multiply-accumulate array performs operation convolution multiply-accumulate. The invention further provides a sparse activation neural network operation data flow basedon the FPGA. The sparse activation neural network operation data flow reconstructs the position of the non-zero activation value and matches the corresponding weight. The neural network accelerator has high data reusability, data movement is reduced, power consumption is saved, unused operation sub-channels and subsequent modules of the operation sub-channels are closed by a gated clock, power consumption is also saved, sparse activation can be efficiently perceived, most of operations carried out by non-zero activation are enabled to be operations carried out, and the operation speed is increased.

Description

technical field [0001] The invention relates to the fields of electronic information and deep learning, in particular to an FPGA-based highly efficient sparse activation-aware neural network accelerator. Background technique [0002] Convolutional neural network (CNN) has become one of the most popular and effective algorithms in computer vision tasks in recent years. Because of its accuracy rate is significantly higher than traditional algorithms, it has been obtained in the fields of image classification, face recognition, and semantic segmentation. Wide range of applications. As the scale of the CNN network model continues to expand, more computing and storage resources are required. Due to the lack of parallel computing resources of the CPU, the large-scale CNN operation has been unable to do what it wants. On the contrary, the GPU with a large number of stream processors has become the The mainstream platform for CNN training and reasoning, but the defect of high energ...

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Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that the utilization rate of sparse activation is relatively low in the prior art using the sparse activation neural network accelerator scheme, and proposes a sparse activation-aware neural network accelerator based on FPGA, which realizes a higher on-chip Data multiplexing, while the data allocation method used reduces power consumption and realizes efficient skipping of 0 values ​​​​in sparse activations

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