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Method for realizing digital decimation filter with CIC structure

A technology for extracting filters and implementation methods, which is applied to digital technology networks, electrical components, impedance networks, etc., can solve the problems of underutilized hardware resources and high hardware overhead, and achieve full use of hardware resources and reduce hardware costs. The effect of spending

Active Publication Date: 2021-03-02
SG MICRO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Multi-stage cascaded adders are the most intuitive way to implement stage-by-stage addition, but the corresponding hardware overhead is relatively large, and hardware resources have not been fully utilized

Method used

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  • Method for realizing digital decimation filter with CIC structure
  • Method for realizing digital decimation filter with CIC structure
  • Method for realizing digital decimation filter with CIC structure

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Embodiment Construction

[0032] Below with the accompanying drawings ( Figure 4-Figure 11 ) to illustrate the present invention.

[0033] The CIC filtering operation is a series of addition and accumulation operations, and the current addition result is only affected by the previous addition result and has nothing to do with other addition operations. The implementation of full adder cascade is relatively simple, direct and easy to understand, but hardware resources cannot be fully utilized. Moreover, the rate at which data flows into the filter is relatively slow, and the time to complete data processing is relatively sufficient. Based on the above characteristics, the present invention redesigns the addition and accumulation execution process in the CIC filtering operation based on the idea of ​​time-division multiplexing, more fully utilizes hardware resources, and reduces hardware overhead. refer to Figure 4 to Figure 11 , implement the realization method of a kind of CIC structure digital de...

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Abstract

The invention relates to a method for realizing a digital decimation filter with a CIC structure, which comprises the following steps of: performing time division multiplexing by utilizing the characteristic that the data operation frequency of each adder is far lower than the frequency of a working clock, and realizing addition operation in a multi-stage CIC cascade structure by using a method that a multipath selection module is matched with one P-bit adder, one P-bit full adder and P 1-bit half adders. Therefore, hardware overhead is reduced or hardware resources are fully utilized.

Description

technical field [0001] The present invention relates to CIC (Cascaded-Integrator-Comb, cascaded integral comb) structure digital decimation filter technology, especially a kind of realization method of CIC structure digital decimation filter, the frequency that utilizes each adder to carry out data operation is far lower than working frequency The characteristics of the clock frequency are used for time-division multiplexing, and the P-bit multi-stage CIC cascaded structure is realized by using a multiplexer module with a P-bit adder, a P-bit full adder, and P 1-bit half adders. The addition operation in, thereby reducing hardware overhead or making full use of hardware resources. Background technique [0002] Generally speaking, a delta-sigma ADC mainly includes two parts: an analog modulator and a digital decimation filter, such as figure 1 shown. The analog modulator oversamples and converts the analog signal to form a bit stream. A digital filter then converts the ser...

Claims

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Application Information

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IPC IPC(8): H03H17/02
CPCH03H17/0202H03H2017/0204
Inventor 张波张利地
Owner SG MICRO