Chip testing method and device, processor chip and server

Abstract

One or more embodiments of the invention disclose a chip test method and device, a processor chip and a server. The chip testing method comprises the steps that: a source file of an ATE vector of automatic testing equipment is acquired, wherein the source file comprises a text file created in a preset compiling language; an ATE vector of a target chip is generated according to the source file; andATE computer test on the target chip is performed according to the ATE vector. The method can shorten the chip test period.

Description

technical field [0001] The invention relates to the technical field of chip automatic testing, in particular to a chip testing method, device, processor chip and server. Background technique [0002] In the design of very large scale digital integrated circuits, especially SoC (System on Chip, system-on-chip), because of its complex functions and complete performance, the entire chip design is generally divided into different IP (Intellectual Property, intellectual property) modules, IP modules Generally refers to a design module with intellectual property rights. The overall design process is to complete the design and verification of a single IP module first, and then integrate it into a large chip. In chip-level testing, between modules and between modules and the outside, communication based on the JTAG (Joint Test Action Group, Joint Test Working Group) protocol and its extensions are most used at present. Therefore, in ATE (Automatic Test Equipment, automatic test eq...

AI Technical Summary

Problems solved by technology

Its output vector file format is various, so, in the ATE test stage, ATE test engineers need to spend more time and cost to get familiar with different design languages, process different test vector files, prolong the test cycle of the chip

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