Signal integrity optimization method and device

Abstract

The invention provides a signal integrity optimization method and device. The method comprises the steps: reading a PCB netlist and a schematic diagram to obtain all network information of a target single board; simulating the target single board by using the network information and obtaining a simulation result for optimizing the physical structure of the target single board; writing corresponding data into the graphical template based on a simulation result; matching the data in the graphical template with the network information; and in response to successful matching of the data in the graphical template and the network information, optimizing the data in the graphical template for the target single board. According to the scheme, design errors caused by interaction of a large number of parameters among engineers can be avoided, meanwhile, the design inspection workload of PCB designers is greatly reduced, and the PCB design efficiency is greatly improved.

Description

technical field [0001] This field relates to the computer field, and more particularly to a method and device for signal integrity optimization. Background technique [0002] One of the most important tasks in the design of high-speed digital signal channels is to ensure the impedance continuity of the channel, that is, the impedance of each component of the entire channel is consistent and changes slightly. The classic high-speed digital signal transmission channel consists of the following parts: Package -> IC Footprint (the hole where the connector is connected to the PCB board) -> Transmission Line -> Connector Footprint -> Connector -> Connector Footprint -> Transmission Line -> IC Footprint->Package. Among them, the impedance continuity of the transmission line part is relatively good. For equipment research and development units, the performance of packages and connectors as purchased parts cannot be changed. The footprint is the main design...

AI Technical Summary

Problems solved by technology

For large-scale high-speed digital boards, due to the different ICs involved, different connectors, different impedances, and different wiring layers, the Footprint optimization methods are different. A typical high-speed digital board may involve dozens or even hundreds of different Each optimization method involves more than 10 variables. These rules are formulated by signal integrity engineers and implemented by PCB engineers. During the process of exchanging these complex information between engineers, information may be lost. In the implementation process of PCB engineers, mistakes will also occur

All the above-mentioned problems lead to a very heavy workload for implementing passive optimization rules on the PCB, and it is prone to errors. Once an error occurs, it is difficult to check

Images