Method and device for controlling AXI bus bandwidth

Abstract

The invention discloses a method and device for controlling AXI bus bandwidth. The method comprises the steps: obtaining a read address effective signal and a read data effective signal from the AXI bus; determining a read delay based on the read address valid signal and the read data valid signal; determining a burst read length based on the protocol of the AXI bus, and determining an expected read period based on the burst read length, the read delay and the expected bandwidth; and setting the read address effective signal period of the AXI bus as an expected read period. The AXI bus bandwidth can be controlled in a universal mode, and the universality and convenience of AXI bus control are improved.

Description

technical field [0001] The present invention relates to the field of data transmission, more specifically, to a method and device for controlling the bandwidth of an AXI bus. Background technique [0002] The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, and it supports unaligned data transmission. At the same time, in burst transmission, only the first address is needed, while separate read and write data channels, and supports outstanding transmission access and out-of-order access, and Easier timing closure. [0003] Because AXI has the characteristics of standardization, general efficiency, etc., FPGAs have begun to use AXI as the interconnection bus between modules on a large scale. AXI is a bus with separate addresses and data, and has its own timing control. The metho...

AI Technical Summary

Problems solved by technology

[0005] There is no effective solution to the problem that the AXI bus bandwidth control method in the prior art is not universal

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