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Multi-chip packaging method

A multi-chip packaging and chip technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to reduce the difficulty of alignment, reduce device costs, and solve alignment problems.

Pending Publication Date: 2021-03-12
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] This application provides a multi-chip packaging method to solve the alignment problem in the preparation process of multi-chip packaging devices

Method used

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Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0030] see figure 1 , figure 1 It is a schematic flow chart of an implementation mode of the multi-chip packaging method of the present application. The above-mentioned multi-chip packaging method specifically includes:

[0031] S101: providing a first wafer 10, the first wafer 10 is provided with a plurality of main chips 100 arranged in a matrix, and non-through scribe grooves 108 are arranged between adjacent main chips 100 (such as image 3 ...

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Abstract

The invention provides a multi-chip packaging method, which comprises the steps: providing a first wafer, the first wafer being provided with a plurality of main chips arranged in a matrix, the firstwafer comprising a front surface and a back surface which are oppositely arranged, the front surface of the main chip being the front surface of the first wafer, the back surface of the main chip being the back surface of the first wafer, and the front surface of the main chip being provided with a plurality of first bonding pads; a spacer with a plurality of openings being arranged on the front face of the first wafer, and a plurality of adjacent first bonding pads from adjacent main chips being correspondingly arranged at the positions of the openings; arranging a bridging chip at each opening, wherein the bridging chip is electrically connected with the plurality of first bonding pads in the opening; and cutting the first wafer to obtain a plurality of packaging bodies, the packaging bodies comprising at least two main chips and at least one bridging chip which are electrically connected. By means of the mode, the alignment problem existing in the chip redistribution process can besolved, and the device cost required by alignment is reduced.

Description

technical field [0001] The present application belongs to the technical field of packaging, and in particular relates to a multi-chip packaging method. Background technique [0002] With the upgrading of electronic products, there are more and more functional requirements for multi-chip packaged devices, and signal transmission between multiple chips in the multi-chip packaged device is also more and more frequent. At present, silicon bridges and other methods are generally used to form an electrical interconnection structure between multiple chips to realize signal transmission. [0003] The existing process of forming the above-mentioned multi-chip packaging device mainly includes: first cutting a single chip from the wafer, then redistributing the multiple chips on the substrate, and then realizing the silicon bridge with the multiple chips at the corresponding positions. electrical connection. The above-mentioned redistribution process requires high alignment accuracy ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/48
CPCH01L21/76895H01L21/486
Inventor 李骏戴颖黄金鑫
Owner NANTONG FUJITSU MICROELECTRONICS