Semiconductor package including conductive bumps
A conductive bump and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc.
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[0019] Hereinafter, exemplary embodiments of the present disclosure will be explained in detail with reference to the accompanying drawings.
[0020] figure 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure. figure 2 is showing figure 1 An enlarged cross-sectional view of part A in . image 3 is showing figure 1 An enlarged cross-sectional view of part B in . Figure 4 is showing figure 1 An enlarged cross-sectional view of part C in .
[0021] refer to Figure 1 to Figure 4 , the semiconductor package 10 may include stacked semiconductor chips. The semiconductor package 10 may include a package substrate 500 , first to fourth semiconductor chips 100 , 200 , 300 , 400 , and a molding member 600 . In addition, the semiconductor package 10 may further include first to fourth conductive bumps 160, 260, 360, 460 and the outer connecting member 530.
[0022] The package substrate 500 may includ...
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