Cache RAM (Random Access Memory) and Reference RAM data exchange controller and implementation method

Abstract

The invention discloses a Cache RAM and Reference RAM data exchange controller and an implementation method, and the data exchange controller is arranged between a Cache RAM and a Reference RAM, and comprises a main control state machine, a data carrying, filtering and judging module, a cache module, a storage access port control module, a register file, an RAM port and an interface module. The data exchange controller filters pre-carried data through the data carrying filtering judgment module, only carries effective data, reduces carrying times, accelerates a data exchange process, saves system bandwidth and power consumption, the data is directly carried from one RAM to another RAM through arrangement of the RAM port, the data exchange controller does not need especially complex data packet conversion, is efficient and concise, is simple in structure and less in occupied resources, saves the transmission bandwidth, accelerates the power-on and power-off process and improves the userexperience when being applied to a system sleep wake-up scene.

Description

technical field [0001] The invention relates to the technical field of SOC chip design and data exchange, and more specifically relates to a CacheRAM and Retention RAM data exchange controller and a method for implementing data swap-in and swap-out. [0002] The present invention has claimed the priority of the invention patent application with the application date of 2020.05.11, the application number of 202010393144.3, and the name of the CacheRAM and Retention RAM data exchange controller and its implementation method. Background technique [0003] At present, with the expansion of low-cost and large-capacity external storage requirements of the Internet of Things and embedded systems, caching low-speed external storage data by adding a dedicated cache controller has gradually become a mainstream technical solution. According to the principle of spatial locality and time locality of data / instruction calls, the Cache controller can reduce frequent data / instruction call-in ...

AI Technical Summary

Problems solved by technology

[0006] In view of this, the present invention provides a data exchange controller for Cache RAM and Retention RAM. The data exchange controller has a simple structure, takes up less resources, can shorten the power-on and power-off time of the system, and solves the problem of existing Cache RAM and Retention RAM data exchange. The process of the switching solution is complicated, the data transfer efficiency of the CPU and the bus is low, and the user experience effect is poor.

Images