Clock generator circuit and clock generating method

Abstract

The clock generating circuit is provided with: a multiplying device (11), a phase synchronizing device (12), and a frequency dividing device (13). The clock generation method has the following steps: a. multiplying the input clock frequency to generate a multiplied clock; b. detecting the phase difference between the clock and the divided clock, only making the multiplied clock with the component corresponding to the phase difference The phase delay of the phase delay, a phase synchronous clock with the same phase as the input clock is generated; c. In the phase synchronous clock, a specific pulse is detected at each fixed cycle, and the phase synchronous clock is divided based on its pulse frequency, the divided clock occurs. Without adding delay elements, etc., a PLL output with a small multiplication number can be generated, and the clock output frequency can be reduced.

Description

technical field [0001] The invention relates to a clock generating circuit and a clock generating method for generating an input clock and a same-period frequency-divided clock or a multiplied clock. Background technique [0002] Figure 10 It is a configuration diagram showing, for example, an existing clock generation circuit shown on pages 29 to 36 of "Information Science and Technology News" Vol.97, No. 106 (issued in June 1997). In the figure, 1 is a multiplying circuit, The frequency of the input clock is multiplied to generate a multiplied clock; 2 is the ring oscillator, which is composed of a digital delay line 3 that delays the multiplied clock; 3 is the digital delay line of the ring oscillator 2; 4 is a counter, which is used to set the digital delay line The delay time of 3; 5 is a phase comparator, which compares the input clock phase and the phase of the feedback clock output from the driver 9, and updates the count value of the counter 7 according to its phas...

AI Technical Summary

Problems solved by technology

[0014] In order to constitute the above existing clock generation circuit, if the multiplication number of the multiplication clock is reduced, the maximum delay time of the digital delay line 8 must be extended to this extent, although it is necessary to arrange a plurality of delay elements and decoders , but due to the large area occupied by the delay element and the decoder, once the multiplication number of the multiplication clock is reduced, the circuit scale will increase, which will increase the cost of the chip. This is the problem

[0015] Also, the problem is that in order to use the multiplication number of the multiplication clock fixedly, once the chip is produced, it is not easy to change the multiplication number

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