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Method for realizing automatic instantiation of top layer of chip system based on python

A chip system and top-level file technology, applied in special data processing applications, CAD circuit design, etc., can solve the problems of cumbersome manual connection work, error-prone, time-consuming, etc., to achieve easy modification, less error-prone, and reduce workload Effect

Pending Publication Date: 2021-05-28
芯河半导体科技(无锡)有限公司
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Problems solved by technology

[0005] The purpose of the present invention is to provide a method based on the python language to realize the automatic instantiation of the top layer of the chip, so as to solve the problems of cumbersome work, more time-consuming, and error-prone defects when the manual connection is instantiated at the top layer

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  • Method for realizing automatic instantiation of top layer of chip system based on python
  • Method for realizing automatic instantiation of top layer of chip system based on python
  • Method for realizing automatic instantiation of top layer of chip system based on python

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Embodiment Construction

[0023] The technical solution of this patent will be further described in detail below in conjunction with specific embodiments.

[0024] see figure 1 , a method for automatically instantiating the top layer of a chip system based on python, including the following steps:

[0025] S1. Collect RTL sub-module interface information and fill in the interface information table, and use sheets to distinguish modules; fill in the sheets of each module in the form including (interface name, signal bit width, interface attributes, signal source module, signal destination module, and top-level signal name);

[0026] S2, use the script written in python language (converted into .exe file) to process the interface information table;

[0027] S3. In the input line in the pop-up window, input the desired module top-level name to generate the top-level file;

[0028] S4. Check the generated check result, that is, the log file, to check whether there is a problem.

[0029] Manipulate the ...

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Abstract

The invention discloses a method for realizing automatic instantiation of a top layer of a chip system based on python, which comprises the following steps of: collecting RTL submodule interface information, filling an interface information table, and distinguishing modules by sheet; processing the interface information table by using a script written by a python language; inputting a desired module top-layer name in an input line in the pop-up window to generate a top-layer file; and checking the generated checking result, namely the log file, and checking whether a problem exists or not. And the script written by the python language can process the interface information table and generate a correct connected top-layer file. According to the method, the top-layer code automatic instantiation script is written by using the understandable python language, and the filled interface information table is processed to generate the top-layer code, so that the workload of top-layer code integration is greatly reduced, the modification is easy, and some signal interface bit widths and interface types are checked, so that errors are not easy to occur.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design verification, in particular to a method for realizing automatic instantiation of the top layer of a chip system based on python. Background technique [0002] Due to the improvement of the chip manufacturing process, from 40nm to 28nm, 16nm, and a large number of commercial applications of 7nm, more and more modules can be integrated in the chip, that is, the circuit complexity is getting higher and higher, which brings more and more challenges to the integration of the top layer of the chip. The greater the difficulty. [0003] At present, the connection method of the top layer in the chip basically adopts a manual method, that is, a manual connection method. The more instantiated modules at the top of the chip, the more workload and error rate it brings. In actual design, for a large-scale chip, when the designer performs top-level instantiation, there may be as many as hundr...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33
CPCG06F30/33Y02D10/00
Inventor 王晓明
Owner 芯河半导体科技(无锡)有限公司
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