52 results about "Sigaction" patented technology

The invention discloses an LLM-based controller CAN communication test method and system, and the method comprises the steps: converting a DBC file into a configuration file, reading a VSS and CAN signal corresponding relation file, and inputting the VSS and CAN signal corresponding relation file to an LLM; calling an LLM model, and generating a test case according to the cue word; constructing an automatic framework to implement an execution function based on a behavior-driven development BDD mode; and associating the generated test case with an execution function in the automation framework, constructing a complete test suite, and operating the test suite to execute a CAN bus communication test. VSS path and CAN Signal verification is carried out on the basis of the controller which already realizes the VSS technology, the test case conforming to the BDD natural language is generated by using the LLM, the test case is directly used as the test script, the step of manually compiling the test case is omitted, the test efficiency is improved, and the test cost is reduced.

Systems, methods, and instrumentalities are disclosed for signaling parameter sets for geometry-based point cloud streams. In example, a device may receive an international organization for standardization base media file format (ISOBMFF) file. The ISOBMFF file may include geometry-based point cloud compression (G-PCC) data that is carried using one or more tracks with sample group description information and sample to group box information. The sample group description information may indicate grouping type information and a plurality of sample group description entries indicating geometry-based volumetric or point cloud parameter set information. The sample to group box information may include one or more sample to group box entries, each with a plurality of entry parameters comprising: the grouping type information, a grouping type parameter, and a sample group description index.

The invention provides a method and a device for verifying and debugging a chip algorithm module. The consistency of a C language reference model and a simulation waveform can be automatically compared and tracked. The method comprises the following steps: constructing a verification environment and generating an fsdb waveform and a C language reference model executable file with debugging information; generating a GDB command and an fsdbreport command based on the configuration information, extracting a variable value and a signal value, and performing consistency comparison; if the comparison is consistent, ending, otherwise, entering signal tracking; in signal tracking, a PyNPI interface is called to forward track a driving signal and analyze a signal value matching condition in a clock period; and if the corresponding value is not matched, generating a new configuration file and circularly executing the debugging process. According to the technical scheme provided by the invention, the root of the problem can be automatically tracked and quickly positioned at the initial verification stage of the algorithm module, the dynamic addition of comparison nodes is supported, and the manual debugging cost is reduced.

The invention provides a relay protection device interface language switching method and system based on a hot loading mechanism, and the method comprises the steps: constructing a variable-length language storage structural body under a C language according to the variable-length text characteristics of multiple languages in a language text file, so as to generate an instantiated object, and further binding an interface element of a relay protection device; under the condition that an operation signal of switching languages of the user interface is detected, obtaining a user target language according to the interface element index so as to read a corresponding language text file; pointing a first-level pointer corresponding to the instantiated object to the read language text file, and pointing a second-level pointer corresponding to the instantiated object to the first-level pointer so as to bind the interface element and the target language text file; analyzing a second-level pointer corresponding to the instantiated object, and mapping the second-level pointer to a first-level pointer corresponding to the instantiated object to obtain target language text information pointed by the first-level pointer. According to the method, interface language switching can be completed without restarting equipment.

Disclosed herein are systems and method for dynamically updating classes in a running application. In one aspect, a method may include identifying an application running within a virtual machine (VM); generating, within the application, a patcher thread for processing patches; instantiating, within the application, a patcher class using a singleton pattern; installing a shutdown hook in the VM to signal the patcher thread to stop operation and release resources during termination of the application; generating a notification that a live patching facility is set up using a system property in the VM; detecting and executing, via the patcher thread, a task to replace an existing version of a class with an updated version of the class at runtime by scanning, using a polling technique, a tasks directory for new class files and finding the updated version of the class.

The present invention discloses an automated integration method for IO signals based on a FADEC operating system. The method comprises the following steps: using Eclipse CDT to parse all structure variables in the As_interface.h file and store them in a linked list A; extracting valid information from each element in the linked list and storing the information in a new linked list B; using a recursive algorithm to convert linked list B into n syntax trees based on pre-defined structure variable names A0 to An-1 for signal interaction between the AS and the OS, with the root nodes of the syntax trees being A0 to An-1, respectively; performing a depth-first search on the generated n syntax trees to automatically generate all signal names; and generating an IO signal integration record file based on a pre-defined IO signal integration template. The method automatically converts nested structures into syntax trees, saving manual time. The method also performs a depth-first search on the syntax trees to automatically generate all IO signals, resulting in a concise and accurate method.

The application provides a monitoring method, device and equipment for a ufs test case and a storage medium, which are applied to a ufs verification platform, the ufs verification platform is connected to a to-be-tested device installed with ufs, the method comprises the following steps: the ufs verification platform generates at least one target instruction based on the ufs test case, sends all the target instructions to the to-be-tested device in sequence, and the to-be-tested device performs target testing based on the target instruction; the ufs verification platform writes all the target instructions and related information into a record file, wherein the related information comprises a logical unit number, a logical block address and a block number of the target instruction; the ufs verification platform generates an end signal and sends the end signal to the to-be-tested device and the record file respectively, the to-be-tested device terminates the target testing, the ufs test case is terminated, and the record file terminates writing. According to the technical scheme of the embodiment of the application, all the target instructions and related information can be recorded, so that the troubleshooting speed and efficiency of the ufs test result are improved.

Embodiments of the present application disclose a file generation method and device, terminal equipment and a storage medium, wherein the method comprises: importing a DBC file / LDF file of a target model; reading the DBC file / LDF file according to a preset target protocol to determine a data frame contained in a corresponding CAN signal / LIN signal; editing a target data frame in the data frame to make the target data frame a medium for sending and / or receiving a target signal; and generating a JSON file corresponding to the target protocol and the target model according to an editing result. Through the above method, the connection between models can be realized without manually writing glue code, the coupling is low, the modularization is easy to realize, and various hardware can be compatible and adapted.

Disclosed herein are techniques for synchronization control of folders in a computing system. In one example, a method includes receiving data representing a signal that indicates a user has interacted with a file in a first folder or has directly interacted with the first folder and a failure to perform a synchronization operation between the first folder at a first server and a corresponding folder at a second server. The method can then include increasing a synchronization priority of the first folder relative to the second folder in accordance with the received signal and synchronizing the first folder at the first server with another corresponding folder at the second server and synchronizing a second folder at the first server with the corresponding folder at the second server in accordance with the increased relative synchronization priority of the first folder relative to the second folder.

The invention relates to the technical field of radio astronomy, and discloses monopulse candidate recognition based on deep learning, comprising the following steps: S1, using Sigproc to convert a Fits file in CRAFTS data into a file in a Filterbank format; s2, generating a group of Cand files by utilizing the Heimdall; s3, converting the signal information in the Cand file into a file in an H5 format by utilizing a Python packet Your; s4, performing feature fusion on two features of frequency-time and DM-time in the H5 file; and S5, inputting the fused features into a model combined with a CNN (Convolutional Neural Network) and a Transform for identification. According to the monopulse candidate body recognition based on deep learning, CRAFTS data are preprocessed through Sigproc, Heimdall and Your tools, an optimized C-C-T-T architecture model is used for recognition, experimental results show that the accuracy rate of 99.59%, the false positive rate of 0.42% and the recall rate of 99.6% are achieved through the method, and the method is remarkably superior to an existing method; according to the method, the accuracy and recall ability of monopulse candidate body identification are improved, and an efficient and accurate research tool is provided for radio astronomy.

The present application relates to the technical field of data pushing, in particular to a method for pushing and real-time previewing and updating of stream file operation based on SSE, which comprises the following steps: collecting a cursor associated sequence, performing comparison, extracting density characteristics, matching and determining a threshold interval, determining length, establishing a pushing load, merging a ratio quota, generating a cursor latching instruction, monitoring an instruction state, grabbing a character bottom layer code, comparing a preset escape sequence, obtaining a truncation identifier, extracting a pre-node end code, combining a full-zero state span value, performing numerical operation, and generating a view rendering signal.In the present application, the transmission slice length is dynamically controlled by frequency comparison combined with interval threshold to construct the load, the quota is compared by table lookup to prevent resource exhaustion and blockage, the bottom layer storage bit XOR span analysis is used to accurately locate the truncation boundary to trigger cross-section rendering, and fixed polling redundant communication overhead and server connection waste are eliminated, thereby ensuring low-latency delivery of batch stream file change data and smooth redrawing and rendering of the front-end page.

The invention belongs to the technical field of integrated circuits, and particularly relates to a triple modular redundancy implementation method based on a shell script. Comprising the following steps: S1, constructing triple modular redundancy of clock and reset, synthesizing by using a DC tool, and outputting a file required by a script; s2, a shell script is used for processing files needed by the script, and three files are obtained; s3, creating a triple modular redundancy module; s4, processing the netlist file corresponding to the sub-level module of the current level in parallel; s5, modifying instantiation ports of all sub-level modules in the netlist file corresponding to the mother-level module of the current level; s6, taking the higher level as the current level and returning to the step S4 until the mother level module of the current level is the top level module; s7, checking whether the clock and reset signals of the top-layer module are consistent with instantiated port signals of the clock and reset of the sublevel module of the top-layer module or not, and if yes, outputting a triple-modular redundancy netlist; otherwise, returning to the step S1; the chip development cycle is shortened, and readability and maintainability are high.

The application discloses a kind of controller CAN communication test method and system based on LLM, DBC file is converted into configuration file, VSS and CAN signal corresponding relationship file is read, as input to LLM;Call LLM model, according to prompt word generation test case;Based on behavior-driven development BDD mode, build automation framework to realize execution function;Correlation generated test case and execution function in automation framework, build complete test suite, run test suite and execute CAN bus communication test.The application is based on the controller that has realized VSS technology to carry out the check of VSS path and CAN Signal, using LLM generates the test case of BDD natural language, test case is directly used as test script, saves the step of manual writing test case, improves test efficiency, reduces test cost.

This invention provides a method and apparatus for verifying and debugging chip algorithm modules, capable of automatically comparing and tracing the consistency between a C language reference model and simulation waveforms. The method includes: constructing a verification environment and generating fsdb waveforms and an executable file of the C language reference model with debugging information; generating GDB and fsdbreport commands based on configuration information, extracting variable values ​​and signal values, and performing consistency comparisons; if a match is found, the process ends; otherwise, signal tracing begins; during signal tracing, the PyNPI interface is called to trace the driving signals forward and analyze the signal value matching within the clock cycle; if no matching value is found, a new configuration file is generated and the debugging process is executed cyclically. The technical solution provided by this invention can automatically trace and quickly locate the root cause of problems in the early stages of algorithm module verification, supports dynamically adding comparison nodes, and reduces manual debugging costs.

Method, apparatus, and system for haptic signal processing are provided. The process may include receiving haptic data in an interchange (HJIF) format based on JavaScript Object Notation (JSON) and receiving a moving picture experts group haptics (MPEG_haptics) object associated with a global haptic experience, the MPEG haptics object in the HJIF format comprising a plurality of reset point timestamps. The process may include rendering effects based on the haptic data in the HJIF format; and may include resetting an output of a renderer based on determining that a current timestamp associated with the global haptic experience is equal to a reset point timestamp in the MPEG haptics object.

The present invention provides a method for generating a communication message union of an ARINC653 system based on an ICD, including: S1. Reading an ICD file to generate an ICD data list; S2. Replacing the system names in the ICD data list with partition masks according to the correspondence between the partition masks and the system names; S3. Verifying the file to verify whether there are duplicate signal names and reserved bit named signals, and displaying the verification result; S4. Generating a communication message union header file for the verified ICD file. The present invention classifies and extracts ICD data for verification based on key common attributes, and generates communication message union header files for each application partition based on the verified ICD, so that the IO partition can access data without depending on specific signal names to implement communication services, thereby decoupling the ICD data from the IO partition code. The present invention improves the ICD change efficiency, avoids introducing human errors, and improves the maintainability of the IO partition software.

The invention provides a method for quickly operating an I2C bus under an Android system, a computer program product and a computer terminal. The method comprises the following steps: writing and loading an I2C device driver in a Linux kernel layer; generating at least one system attribute node for I2C communication in the I2C device driver; obtaining read-write operation of an upper-layer application program of the Android system on the system attribute node through a standard file read-write interface; and the I2C device driver monitors and analyzes data of an upper-layer application program of the Android system for performing read-write operation on a system attribute node and a specified slave device address, and converts the data and the specified slave device address into a corresponding I2C bus protocol signal to complete communication with the specified slave device. In this way, all I2C operations can be completed only by using the most basic and most universal standard file read-write interface read-write API in the Android SDK, and the universality of the I2C bus in the Android system is improved.

An embedded debugging method and apparatus, and a system. The method comprises: pre-configuring trigger information, the trigger information comprising a trigger data type, comparison content, and a trigger condition; on the basis of the pre-configured trigger data type, monitoring, by means of an information monitoring module, information received or sent by a processor and / or another functional module; by means of a comparison module, comparing the monitored corresponding information with the preset comparison content; and when the comparison result satisfies the preset trigger condition, performing corresponding processing. By using a real-time monitoring method, on the basis of triggering a preset trigger condition, corresponding information is stored or an interrupt signal is generated when the preset trigger condition is met, thereby quickly locating a program address of a related problem during debugging, achieving the purpose of high-efficiency debugging, or storing a related program address, achieving the purpose of software testing for a corresponding program, or storing related time information and testing time performance of a corresponding program, achieving the purpose of quickly optimizing the program.

The invention discloses a firmware file burning method and a system-level chip, which can be used in the field of chip burning, and the method comprises the following steps: firstly, obtaining a current sub-data packet of a firmware file and an initial cyclic redundancy check value corresponding to the current sub-data packet; then, calculating a current cyclic redundancy check value corresponding to the current sub-data packet; and finally, comparing the consistency of the initial cyclic redundancy check value and the current cyclic redundancy check value. If yes, a burning success signal is sent to the host device so as to execute burning of the next sub-data packet; and if not, sending a burning failure signal to the host equipment so as to re-execute burning of the current sub-data packet. Therefore, when each sub-data packet is burnt, the burning result of the sub-data packet is verified, so that in the burning process of the firmware file, the burning result of each sub-data packet is monitored in real time, the amount of data needing to be secondarily burnt after burning errors is reduced, and the burning efficiency of the firmware file is improved.

The application relates to an automatic extraction and error injection ECC verification method and device, a module integrated with an ECC function and a bus interface signal in a chip to be verified are acquired through a script, a signal path capable of monitoring transmission and error injection is obtained, verification parameters of a test case file are generated, and verification of the ECC function integrated in each module is realized. The extraction process of signal information is simplified by using a built-in script tool of verdi and a python script, the efficiency of verification is improved, and the reusability and sufficiency of verification are improved.

The invention discloses an Excel-to-DBC file conversion method and system based on intelligent verification and multi-version adaptation, and the method comprises the steps: automatically recognizing an Excel template version of an Excel file through a feature matching algorithm, calling a verification rule base corresponding to the recognized Excel template version, carrying out the multi-level verification of the Excel file, and carrying out the multi-level verification of the Excel file through a Motora byte order conversion algorithm. And converting the signal in the LSB byte order format into a signal in an MSB byte order format, preprocessing the signal converted into the MSB byte order format to obtain a file conforming to the DBC format, and expanding the file conforming to the DBC format to multi-format adaptive output. According to the method, the Excel template version of the Excel file is automatically recognized, the multi-level verification effect is good, the accuracy of start bit calculation is ensured through a professional Motora byte order conversion algorithm, multiple output formats are supported, function extension is facilitated through modular design, rapid access of the new template version and the output formats is supported, and the user experience is good.

The invention belongs to the field of electric signal acquisition, and particularly relates to a sampling method and system based on non-real-time embedded Linux. Comprising the following steps: (1) receiving and storing a sampling signal by an FPGA (Field Programmable Gate Array), and triggering ARM (Advanced RISC Machines) hard interrupt of an embedded Linux after a set time length; 2) after the ARM hard interrupt is triggered, the ARM responds to the interrupt so as to read all sampling signals stored in the FPGA within a set time length; 3) after reading all the sampling signals stored in the FPGA, the ARM sends a receiving response signal to the FPGA so as to inform the FPGA that the sampling signals are read completely; and 4) after the FPGA receives a receiving response signal, closing the ARM hard interrupt, re-performing the operations of the steps 1)-2), combining all the read sampling signals stored in the FPGA within the set time length with the previously read sampling signals into a group of continuous sampling signals, then sending the receiving response signal to the FPGA to inform the FPGA that the sampling signals are read completely, and then repeating the step 4).

The invention discloses an automatic packaging method and system for application services. The method comprises the steps that an ARXML file and a DBC file are obtained; performing signal analysis on the ARXML file and the DBC file to obtain a model external interface; creating an interface model framework and an interface type definition file corresponding to the interface model framework according to the ARXML file; generating a scheduling code based on the ARXML file and a preset integrated scheduling rule thereof; and packaging the model external interface, the interface model framework, the interface type definition file and the scheduling code. According to development requirements, the interface is automatically generated according to the signal, the RTE code is automatically generated, meanwhile, the code is automatically generated, and the unified development environment not only improves the development efficiency, but also realizes seamless integration and interoperability between different protocols.

The invention discloses an automatic file synchronization method based on a code hosting platform and a software development system.The method comprises the steps that an event trigger is configured in a continuous integration / continuous delivery assembly line of the code hosting platform, and the event trigger is used for responding to a file change event of a code library of the code hosting platform and generating a trigger signal; based on an automatic execution node in the code hosting platform, detecting a code library according to the trigger signal to obtain a change file; performing format conversion on the changed file to generate a target format file; and synchronously submitting the target format file to a code library. According to the method, the file change is automatically detected, the conversion process is triggered, manual operation is completely replaced, omission or errors caused by the fact that developers forget to execute the conversion or submission step are eliminated, especially in a multi-person cooperation environment, the frequency and complexity of manual code merging are reduced through automatic file change detection and synchronous submission, and the efficiency of code merging is improved. And the code merging efficiency and accuracy are improved.

The application discloses a shortcut key implementation method, a computing device and a storage medium, and comprises the following steps: constructing a compatibility module in the computing device; running an application program in a first operating system through the compatibility module, the application program being adapted to run in a second operating system; generating a second shortcut key file according to a target operation to be performed in the application program, and registering the second shortcut key file in the first operating system; generating a second input instruction according to the second shortcut key file and an input signal of an input device in response to receiving the input signal; and sending the second input instruction to the application program so as to complete the target operation by executing the second input instruction through the application program. By registering the second shortcut key file in the operating system, the application program can still normally use the shortcut key to complete the target operation when the application program is executed in the operating system which is not completely adapted, and the use experience of a user when using the operating system to run the application program which is not completely adapted is improved.

The application discloses a kind of based on FPGA cloud platform's hardware simulation verification process implementation method, client obtains the source code file of user design, compiles integrated source code file, generates instance tree and resource occupation situation;Global instance is specified, and the instance of user design is split into small instance module;According to the instance module of splitting, the signal flow graph between different modules is generated;User is divided into different FPGA under the operation of client by following certain principle and split instance module;The attribute of signal between different FPGA is specified by client, and connection port is configured, and probe is inserted;FPGA sub-project top file is generated, and sub-project bit stream is generated by compiling, and after encryption, it is sent to cloud platform server;Trigger condition is configured in client, and cloud platform deploys running simulation program, debugs and looks waveform data and sends to client display.Satisfy the verification demand of large-scale chip design hardware simulation, and protect the intellectual property right of user.

The invention discloses an Excel data exporting method and device. The Excel data exporting method is executed in the same Java virtual machine in sequence. The method comprises the steps that a level signal receives original data and places the original data into a temporary magnetization file; loading the JSON mapping file with the version number into a memory heap; analyzing and mapping to generate an XSSFWorkbook template object; a field level ConcurentHashMap style cache is established, and data filling is completed; when the row count reaches a hardware constant, newly establishing a sheet, writing the charge image into a disk in a streaming manner, and immediately releasing the memory of the sheet; finally, the magnetization direction sequence is converted into optical pulses through DMA, the optical pulses are returned to a client side, and meanwhile the TRIM erases the temporary file. According to the method, under the condition that an SXSSF is not used, complex cell merging and low memory occupation are considered, version rollback is supported, the style cache is synchronously destroyed along with the sheet life cycle, and rapid, flexible and idempotent export of a large file is achieved.

The invention relates to an automatic generation method and device for a verilog file controlled by a PAD, and the method comprises the steps: building a standard cell library through the PAD logic related to a technology in advance, and enabling a top layer to directly call a standard cell in the standard cell library to carry out the instantiation of the standard cell of the PAD logic; in the actual use process, an excel file controlled by a PAD can be compiled according to the position where the PAD needs to be placed and an interface signal of a standard unit of PAD logic, and then the excel file is processed by utilizing a python script to automatically generate a synthesizable verilog file, so that the design complexity of a PAD control circuit is greatly reduced, optimization and maintenance of a front end and placement and connection of a rear end are facilitated, and the practicability of the PAD control circuit is improved. And the high consistency of the final circuit and the instruction file is ensured.

The invention discloses a software file compression method and device, a storage medium and computer equipment, and the method comprises the steps: responding to a compression signal of a target software file, obtaining file attribute information, compression demand information and file use information of the target software file, and splitting the target software file into a plurality of semantic blocks; based on the file attribute information, the compression demand information and the file use information, determining a compression strategy adapted to the target software file; based on the compression strategy, compressing each semantic block, in the compression process, judging whether the current semantic block meets a compression interruption condition or not, and if yes, interrupting the compression process of the current semantic block to release thread resources; and in response to a continuous compression signal of the current semantic block, identifying a compression interruption position of the current semantic block, and continuing to compress the remaining uncompressed file data in the current semantic block from the compression interruption position.