24 results about "Sigaction" patented technology

The application provides a monitoring method, device and equipment for a ufs test case and a storage medium, which are applied to a ufs verification platform, the ufs verification platform is connected to a to-be-tested device installed with ufs, the method comprises the following steps: the ufs verification platform generates at least one target instruction based on the ufs test case, sends all the target instructions to the to-be-tested device in sequence, and the to-be-tested device performs target testing based on the target instruction; the ufs verification platform writes all the target instructions and related information into a record file, wherein the related information comprises a logical unit number, a logical block address and a block number of the target instruction; the ufs verification platform generates an end signal and sends the end signal to the to-be-tested device and the record file respectively, the to-be-tested device terminates the target testing, the ufs test case is terminated, and the record file terminates writing. According to the technical scheme of the embodiment of the application, all the target instructions and related information can be recorded, so that the troubleshooting speed and efficiency of the ufs test result are improved.

Embodiments of the present application disclose a file generation method and device, terminal equipment and a storage medium, wherein the method comprises: importing a DBC file / LDF file of a target model; reading the DBC file / LDF file according to a preset target protocol to determine a data frame contained in a corresponding CAN signal / LIN signal; editing a target data frame in the data frame to make the target data frame a medium for sending and / or receiving a target signal; and generating a JSON file corresponding to the target protocol and the target model according to an editing result. Through the above method, the connection between models can be realized without manually writing glue code, the coupling is low, the modularization is easy to realize, and various hardware can be compatible and adapted.

The present application relates to the technical field of data pushing, in particular to a method for pushing and real-time previewing and updating of stream file operation based on SSE, which comprises the following steps: collecting a cursor associated sequence, performing comparison, extracting density characteristics, matching and determining a threshold interval, determining length, establishing a pushing load, merging a ratio quota, generating a cursor latching instruction, monitoring an instruction state, grabbing a character bottom layer code, comparing a preset escape sequence, obtaining a truncation identifier, extracting a pre-node end code, combining a full-zero state span value, performing numerical operation, and generating a view rendering signal.In the present application, the transmission slice length is dynamically controlled by frequency comparison combined with interval threshold to construct the load, the quota is compared by table lookup to prevent resource exhaustion and blockage, the bottom layer storage bit XOR span analysis is used to accurately locate the truncation boundary to trigger cross-section rendering, and fixed polling redundant communication overhead and server connection waste are eliminated, thereby ensuring low-latency delivery of batch stream file change data and smooth redrawing and rendering of the front-end page.

The invention belongs to the technical field of integrated circuits, and particularly relates to a triple modular redundancy implementation method based on a shell script. Comprising the following steps: S1, constructing triple modular redundancy of clock and reset, synthesizing by using a DC tool, and outputting a file required by a script; s2, a shell script is used for processing files needed by the script, and three files are obtained; s3, creating a triple modular redundancy module; s4, processing the netlist file corresponding to the sub-level module of the current level in parallel; s5, modifying instantiation ports of all sub-level modules in the netlist file corresponding to the mother-level module of the current level; s6, taking the higher level as the current level and returning to the step S4 until the mother level module of the current level is the top level module; s7, checking whether the clock and reset signals of the top-layer module are consistent with instantiated port signals of the clock and reset of the sublevel module of the top-layer module or not, and if yes, outputting a triple-modular redundancy netlist; otherwise, returning to the step S1; the chip development cycle is shortened, and readability and maintainability are high.

An embedded debugging method and apparatus, and a system. The method comprises: pre-configuring trigger information, the trigger information comprising a trigger data type, comparison content, and a trigger condition; on the basis of the pre-configured trigger data type, monitoring, by means of an information monitoring module, information received or sent by a processor and / or another functional module; by means of a comparison module, comparing the monitored corresponding information with the preset comparison content; and when the comparison result satisfies the preset trigger condition, performing corresponding processing. By using a real-time monitoring method, on the basis of triggering a preset trigger condition, corresponding information is stored or an interrupt signal is generated when the preset trigger condition is met, thereby quickly locating a program address of a related problem during debugging, achieving the purpose of high-efficiency debugging, or storing a related program address, achieving the purpose of software testing for a corresponding program, or storing related time information and testing time performance of a corresponding program, achieving the purpose of quickly optimizing the program.

The invention discloses an Excel-to-DBC file conversion method and system based on intelligent verification and multi-version adaptation, and the method comprises the steps: automatically recognizing an Excel template version of an Excel file through a feature matching algorithm, calling a verification rule base corresponding to the recognized Excel template version, carrying out the multi-level verification of the Excel file, and carrying out the multi-level verification of the Excel file through a Motora byte order conversion algorithm. And converting the signal in the LSB byte order format into a signal in an MSB byte order format, preprocessing the signal converted into the MSB byte order format to obtain a file conforming to the DBC format, and expanding the file conforming to the DBC format to multi-format adaptive output. According to the method, the Excel template version of the Excel file is automatically recognized, the multi-level verification effect is good, the accuracy of start bit calculation is ensured through a professional Motora byte order conversion algorithm, multiple output formats are supported, function extension is facilitated through modular design, rapid access of the new template version and the output formats is supported, and the user experience is good.

The invention belongs to the field of electric signal acquisition, and particularly relates to a sampling method and system based on non-real-time embedded Linux. Comprising the following steps: (1) receiving and storing a sampling signal by an FPGA (Field Programmable Gate Array), and triggering ARM (Advanced RISC Machines) hard interrupt of an embedded Linux after a set time length; 2) after the ARM hard interrupt is triggered, the ARM responds to the interrupt so as to read all sampling signals stored in the FPGA within a set time length; 3) after reading all the sampling signals stored in the FPGA, the ARM sends a receiving response signal to the FPGA so as to inform the FPGA that the sampling signals are read completely; and 4) after the FPGA receives a receiving response signal, closing the ARM hard interrupt, re-performing the operations of the steps 1)-2), combining all the read sampling signals stored in the FPGA within the set time length with the previously read sampling signals into a group of continuous sampling signals, then sending the receiving response signal to the FPGA to inform the FPGA that the sampling signals are read completely, and then repeating the step 4).

The application discloses a shortcut key implementation method, a computing device and a storage medium, and comprises the following steps: constructing a compatibility module in the computing device; running an application program in a first operating system through the compatibility module, the application program being adapted to run in a second operating system; generating a second shortcut key file according to a target operation to be performed in the application program, and registering the second shortcut key file in the first operating system; generating a second input instruction according to the second shortcut key file and an input signal of an input device in response to receiving the input signal; and sending the second input instruction to the application program so as to complete the target operation by executing the second input instruction through the application program. By registering the second shortcut key file in the operating system, the application program can still normally use the shortcut key to complete the target operation when the application program is executed in the operating system which is not completely adapted, and the use experience of a user when using the operating system to run the application program which is not completely adapted is improved.

The application discloses a kind of based on FPGA cloud platform's hardware simulation verification process implementation method, client obtains the source code file of user design, compiles integrated source code file, generates instance tree and resource occupation situation;Global instance is specified, and the instance of user design is split into small instance module;According to the instance module of splitting, the signal flow graph between different modules is generated;User is divided into different FPGA under the operation of client by following certain principle and split instance module;The attribute of signal between different FPGA is specified by client, and connection port is configured, and probe is inserted;FPGA sub-project top file is generated, and sub-project bit stream is generated by compiling, and after encryption, it is sent to cloud platform server;Trigger condition is configured in client, and cloud platform deploys running simulation program, debugs and looks waveform data and sends to client display.Satisfy the verification demand of large-scale chip design hardware simulation, and protect the intellectual property right of user.

The invention discloses an Excel data exporting method and device. The Excel data exporting method is executed in the same Java virtual machine in sequence. The method comprises the steps that a level signal receives original data and places the original data into a temporary magnetization file; loading the JSON mapping file with the version number into a memory heap; analyzing and mapping to generate an XSSFWorkbook template object; a field level ConcurentHashMap style cache is established, and data filling is completed; when the row count reaches a hardware constant, newly establishing a sheet, writing the charge image into a disk in a streaming manner, and immediately releasing the memory of the sheet; finally, the magnetization direction sequence is converted into optical pulses through DMA, the optical pulses are returned to a client side, and meanwhile the TRIM erases the temporary file. According to the method, under the condition that an SXSSF is not used, complex cell merging and low memory occupation are considered, version rollback is supported, the style cache is synchronously destroyed along with the sheet life cycle, and rapid, flexible and idempotent export of a large file is achieved.

The invention discloses a software file compression method and device, a storage medium and computer equipment, and the method comprises the steps: responding to a compression signal of a target software file, obtaining file attribute information, compression demand information and file use information of the target software file, and splitting the target software file into a plurality of semantic blocks; based on the file attribute information, the compression demand information and the file use information, determining a compression strategy adapted to the target software file; based on the compression strategy, compressing each semantic block, in the compression process, judging whether the current semantic block meets a compression interruption condition or not, and if yes, interrupting the compression process of the current semantic block to release thread resources; and in response to a continuous compression signal of the current semantic block, identifying a compression interruption position of the current semantic block, and continuing to compress the remaining uncompressed file data in the current semantic block from the compression interruption position.

The application provides a data reading method and system for a mirror copy of a distributed parallel file system. When a primary copy fails, the application first intercepts errors to avoid direct business interruption, converts the failure signal into a trigger condition for automatic recovery, and then interacts with a metadata server to complete the degradation of the failed copy and the promotion of the healthy copy, update the global metadata view of the file, avoid subsequent requests from continuously accessing the failed node, seamlessly redirect the read request to the healthy copy to complete data reading, the entire process is not perceived by the upper layer application, millisecond-level self-healing of the failure is achieved, the access capability of the redundant copy is released, and the business interruption problem caused by the single-point failure of the primary copy is solved.

The application discloses a code file generation method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits, and comprises the following steps: acquiring a first code file corresponding to a first programming language, at least one code template corresponding to a second programming language, and operation information collection rules. The first code file written in the first programming language performs a first-level verification operation on a to-be-tested instance. In the verification operation process, operation information of the to-be-tested instance is collected according to signal and operation information collection rules between the to-be-tested instance and a target device. According to the operation information, a log is generated. After the first-level verification operation is completed, a second code file in the second programming language is automatically generated according to the log and a preset code template in the second programming language, so that the second code file can be directly used for a second-level verification operation. In this way, a technical personnel is not required to write a file in the second programming language, and the efficiency of the verification work is greatly improved.

The invention discloses an underlying software and simulink model combination method and an MBD tool chain design method, and relates to the technical field of automobile electronic embedded software development, and the method comprises the following steps: constructing a lightweight structure on a software architecture level; generating a common header file data dictionary; setting an input or output signal; a polling interface of the functional module is incorporated into time slice scheduling logic; and completing automatic integration from the function model to the executable code. According to the method, the deployment process from the model to the executable code is simplified, the development threshold and cost are remarkably reduced, the development efficiency, the code reusability and the iteration speed are improved, and meanwhile good reliability and maintainability are kept.

The invention provides a Qt-based Linux software development system, and relates to the field of computer software architecture design, and the Linux software development system comprises a configuration module which is used for providing multi-source configuration fusion and verification fault tolerance; the communication module provides a multi-communication-mode decoupling integration service and is used for expansion, data encapsulation and transceiving; the task management module is used for providing a unified task development standard and a module cooperation mechanism, performing cross control and arrangement combination control on tasks, and realizing task state linkage among multifunctional modules based on a Qt signal slot mechanism; the data storage module is used for uniformly standardizing and storing multiple types of data and monitoring the data; and the interface development module is used for providing a hierarchical structure and configuring interface development. According to the method, team collaboration development efficiency can be remarkably improved, code reuse and data access specifications are enhanced, team collaboration and software performance are optimized, a flexible expansion interface is provided, and development efficiency and performance are considered.

The invention provides a JTAG interface verification assembly supporting an SVF file format, and relates to the technical field of integrated circuit verification, and the JTAG interface verification assembly is mainly characterized in that an SVF file analysis module is used for reading and analyzing an input SVF file, and extracting test vector information in the SVF file; the JTAG time sequence generation module is used for generating a time sequence signal according to the test vector information; the UVM driver interface module is used for transmitting a time sequence signal to a JTAG interface of the integrated circuit to be tested; the control module is used for generating excitation and is responsible for starting SVF file analysis, scheduling JTAG time sequence generation and interacting with the UVM environment. The method can support SVF file format input, can convert the SVF file format input into a standard JTAG time sequence signal to be issued and executed, can efficiently and flexibly achieve functional verification and testing of an integrated circuit, has the advantages of expandability and high precision, can be widely applied to the field of integrated circuit design, verification and testing, and has wide application prospects. The method is especially suitable for the design of a complex digital system requiring an efficient and automatic test process.

The invention discloses a test script automatic generation method and system and a program product, and relates to the technical field of automatic test.The method comprises the steps that source files are loaded one by one through a source file loading class in a singleton mode; analyzing MCU signal data, test case data, alarm pop-up window data, alarm lamp data and power supply data from source files by utilizing a plurality of source file analysis threads in the thread pool; automatically generating a test environment initialization command, a test result check command and a function test command by an automatic command generation function according to the analyzed various data; and classifying or combining various automatically generated commands, transmitting the commands to a serial port, and running a test. According to the test script automatic generation method and system and the program product provided by the invention, the command and the script required by the instrument function test can be automatically generated according to the original data, and the generation efficiency is greatly improved.

The application discloses a kind of based on function call stack backtracking and defect management method of crash sample clustering, comprising: subscribing and collecting Java exception, ANR and Native crash signal, record time stamp, thread name, device fingerprint, APK / SDK version meta information, it is encapsulated as "crash sample unit";Load corresponding version mapping file and NDK (Native Development Kit) symbol, restore method name and source code line number, and execute path normalization and noise frame clipping;Splice scattered call segment, generate complete trigger path;Based on exception type, TopK key frame, trigger path hash and environment abstract, generate robust signature;Similarity calculation and configurable threshold clustering are carried out in signature space, and same source or similar crash is merged into "crash cluster";Representative sample is selected to each cluster, combined with event sequence, page state and life cycle track, automatically generate replayable PoC script and structured report.The application can improve the accuracy of defect deduplication and aggregation and enhance defect reproduction and positioning ability.

The application discloses a kind of based on model development's software architecture generation method, device, terminal and storage medium, belong to computer technical field, including: the software relevant data is divided into corresponding to different functional requirements and corresponding principle several initial function modules;Several initial function modules are defined to signal input and output interface, and the interface attribute and interface interaction relationship are determined to obtain several to be built function modules;According to several the software implementation model framework of to-be-built function module is obtained;According to several the empty architecture model of meeting the attribute of automobile open system architecture of to-be-built function module is obtained, and is associated with software implementation model framework;The interface of software implementation model framework and empty architecture model is associated and matched to obtain the architecture code file package of software architecture.The application has the characteristics of high efficiency, shorter development cycle and strong software reliability.

The application belongs to the technical field of simulation, and particularly relates to a firmware coverage rate determination method and device, a storage medium and equipment. The method comprises the following steps: obtaining a global address range according to a firmware logic file; wherein the firmware logic file is a file for storing firmware execution logic related information, and the global address range is used for reflecting a storage interval of the firmware execution logic; obtaining a target firmware address according to a firmware signal file; wherein the firmware signal file is a file for storing response signal related information, the response signal is generated in response to the firmware executing instruction information in the firmware logic file, and the target firmware address is used for reflecting a storage position of the firmware signal, and the global address range comprises the target firmware address; determining a firmware coverage rate based on the target firmware address and the global address range; wherein the firmware coverage rate is used for reflecting an execution rate of the firmware execution logic; and the application can improve the debugging efficiency between software and hardware.

The invention discloses an automatic test method and system for a CAN interface of an electric control product. The method comprises the following steps: creating a modular test table to define a corresponding relation between a CAN signal and an electric control internal variable; automatically analyzing the table and a CAN database DBC file through a Python script, and generating a use case set for testing the maximum value, the minimum value and the intermediate value of the signal and a mapping file; the test management platform loads and executes the use case, and automatically calls the bus tool and the calibration tool to cooperatively complete the bidirectional test of the electric control sending and receiving function; and finally, automatically judging a result. According to the method, full-process automation of CAN interface testing is achieved, the testing efficiency, accuracy and coverage rate are greatly improved, different items can be rapidly adapted only by modifying table content by creating the modular testing table, high reuse of a testing framework is achieved, and the testing development and maintenance cost is remarkably reduced.

The application discloses a ladder diagram program compiling method, relates to the field of programmable logic controller (PLC) ladder diagram program compiling in the industrial control field, and aims to improve the efficiency of ladder diagram program compiling. Step 1, Links sorting, analyzing the transmission direction of the connected signal, and sorting all the connections; step 2, allocating the number for items and sorting according to the number; step 3, syntax and semantic checking; step 3.1, module syntax and semantic checking; step 3.2, syntax and semantic checking of input pins; step 3.3, syntax and semantic checking of output pins; step 4, giving a prompt in the case of error in the above syntax and semantic checking, and entering the intermediate program generation stage in the case of no error, generating intermediate files ldo and.c files, and finally calling gcc to compile into machine recognizable.o files. The application avoids the long module type judgment and the compiling process in the traditional compiling process, lets each module object realize the compiling function by itself, does not compile the unused module, and clearly distributes the responsibilities.

Operating program writing system (10) that writes an operating program of a system (1) consisting of a peripheral device and a robot (2), wherein the operating program writing system comprises: a block memory section (11) configured to store a plurality of blocks, each of which is a unit of work constituting the operating program, a selection section (12) which is configured to select by it any number of blocks to be combined to form the operating program from the multitude of blocks stored in the block memory section, a display section (13) configured to display a path diagram in which any number of blocks selected by the selection section are arranged according to a user-defined order such that they form the operating program, a selection and input section (14) which is configured to accept the selection of at least one block from among any number of blocks displayed on the display section and through which arguments of the selected at least one block can be entered, a sequence section (15) which is set up to arrange sequence buttons (A) for any number of blocks on the display section and to allow, through the selection and input section, only those blocks that correspond to the sequence buttons and whose sequence buttons have been pressed, a write section (16) configured to use i) any number of blocks selected by the selection section, and ii) the input argument of the at least one block selected by the selection and input section as the basis for writing the operating program, and a setting section (17) which is set up to parse an existing operating program and to set a variety of blocks and arguments contained in the blocks from the existing operating program, wherein: - the blocks include a variety of position blocks (P1, P2, P3, P4) that teach which positions the robot moves to, and a variety of logic blocks (L1, L2, L3, L4, L5, L6) that teach which types of operations are to be performed, - the multitude of blocks selected by the selection section includes at least one positional block and at least one logical block, - the operating program consists of a multitude of lines, with the set section set up to evaluate the attribute of each line as either a logic attribute, a control signal attribute, or a position attribute, and - the set section is further set up to i) write a line of a position attribute and a line of a logic attribute as independent blocks and ii) assign lines of a control signal attribute that follow a line of a logic attribute to the same block as the related line of the logic attribute, in order to set the logic blocks and the position blocks and to set the arguments contained in the blocks.