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Method and system for automatically generating netlist file for testing software and hardware

A netlist file, software and hardware technology, applied in the system field of automatically generating netlist files for testing software and hardware, and netlist files, can solve problems such as high professional technical requirements and time-consuming, and reduce technical requirements. , Improve test efficiency and improve test coverage

Active Publication Date: 2020-07-10
EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] During the testing process of FPGA EDA tools, testers need to verify the correctness of the process of packing, layout, wiring, and code generation, and they need to have enough and diverse test cases, that is, circuit design, which has a great impact on the professional skills of testers. The requirements are very high, and it will take a lot of time to prepare the test circuit

Method used

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  • Method and system for automatically generating netlist file for testing software and hardware
  • Method and system for automatically generating netlist file for testing software and hardware
  • Method and system for automatically generating netlist file for testing software and hardware

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Embodiment Construction

[0022] Such as Figure 5 As shown, this automated method for generating netlist files for testing hardware and software includes the following steps:

[0023] (1) Generate a batch of signals through scripts;

[0024] (2) BLE structure analysis and netlist information establishment: Randomly select the input port of the BLE lookup table and trigger from the signal in step (1), and determine the output of the entire BLE according to the port connected at the same time, and set it as the output Define an output signal, and merge all output signals into a signal set, and use it as an input signal to facilitate connection with other logic structures;

[0025] (3) IO structure analysis and netlist information establishment: analyze the IO structure, obtain all input, output ports, and attribute parameters of the IO; for the division of signal sets used in steps (1) and (2): In the first case, the source is IO and the output signal of the input IO; in the second case, the external ...

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Abstract

The invention discloses a method and a system for automatically generating a netlist file for testing software and hardware, which can effectively improve the testing efficiency of FPGA software, canreduce the technical requirements on testing personnel and can greatly improve the testing coverage rate of the FPGA software. The method comprises the following steps: (1) generating a batch of signals through scripts; (2) performing BLE structure analysis and netlist information establishment; (3) performing IO structure analysis and netlist information establishment; and (4) sequentially writing the related information into the netlist file according to the structural characteristics of the netlist file, and establishing the netlist file.

Description

technical field [0001] The invention relates to the technical field of software testing in the field of programmable logic devices, in particular to a method for automatically generating netlist files for testing software and hardware, and a system for automatically generating netlist files for testing software and hardware. Background technique [0002] The main function of the FPGA EDA (Field-Programmable Gate Array Electronics DesignAutomation, field programmable gate array electronic design automation) tool is to convert the specific circuit design into a netlist file (the netlist file is a file describing the connection relationship of the circuit, generally It is a text file. Simply put, it translates the schematic diagram into a text file. The file will contain the device's label, package, and connection relationship. Import this file into the PCB editor, and the editor will take out the corresponding package from the package library. , give the corresponding label an...

Claims

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Application Information

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IPC IPC(8): G06F11/36
CPCG06F11/3676G06F11/3648Y02D10/00
Inventor 冯苏红徐维涛
Owner EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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