Cross-clock-domain time sequence constraint file generation method and device and medium

Abstract

The invention discloses a cross-clock-domain time sequence constraint file generation method and device and a medium, which are applied to a field programmable gate array (FPGA). The method comprises:determining a pre-written cross-clock-domain synchronous processing module and a cross-clock-domain time sequence constraint command; generating a script according to the clock domain crossing time sequence constraint command; and running the script, retrieving each module contained in the FPGA, determining a signal needing to be subjected to cross-clock domain processing according to the cross-clock domain synchronous processing module, and outputting a cross-clock time sequence constraint command corresponding to the signal to generate a time sequence constraint file. Aiming at a method formanually writing a cross-clock-domain time sequence signal time sequence constraint file in an existing FPGA design process, the method for highly automatically generating the cross-clock-domain timesequence constraint file is completed through a scripting language. The method is convenient to implement, simple in process, efficient and stable, the time for manually constraining the files according to the time sequence can be greatly shortened, and the FPGA research and development efficiency is improved.

Description

technical field [0001] The present application relates to the field of FPGA design, in particular to a method, device and medium for generating a timing constraint file across clock domains. Background technique [0002] At present, the electronic information technology industry is developing rapidly, and the performance requirements for special-purpose chips are getting higher and higher. With the rapid progress of integrated circuit manufacturing technology, the complexity of integrated circuits is increasing exponentially, and the R & D and production cycle is greatly extended, which cannot be well adapted to Changing market demands. Field Programmable Gate Array (Field Programmable Gate Array, FPGA) provides a method that can flexibly implement circuits, and balances the contradiction between product development cycle and product performance. [0003] In the prior art, on the one hand, the FPGA design scale is getting larger and larger, and the number of signals is incr...

AI Technical Summary

Problems solved by technology

Therefore, the synchronization of signals in different clock domains is very important for the correct function of the design, and manually writing the corresponding constraint files of cross-clock domain signals is a very tedious, time-consuming and error-prone work.

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