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Double-ended data transfer circuit and memory

A data transmission circuit and data transmission technology, applied in the direction of digital memory information, static memory, information storage, etc., to achieve the effect of ensuring reliability, saving power consumption, and reducing the number of data inversions

Active Publication Date: 2022-04-26
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the existing memory still has room for improvement in terms of power consumption and reliability. It is urgent to design a memory that can reduce power consumption and improve storage reliability, and further improve the overall performance of the existing memory to face various applications. Scenario requirements

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  • Double-ended data transfer circuit and memory
  • Double-ended data transfer circuit and memory
  • Double-ended data transfer circuit and memory

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Embodiment Construction

[0036] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of storage units is getting higher and higher; at the same time, various applications have higher and higher requirements for DRAM performance, power consumption and reliability. However, the existing memory still has room for improvement in terms of power consumption and reliability. It is urgent to design a memory that can reduce power consumption and improve storage reliability, and further improve the overall performance of the existing memory to face various applications. scene requirements.

[0037] In order to solve the above problems, an embodiment of the present application provides a double-ended data transmission line for writing data and reading data to the storage unit, including: a first global dat...

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Abstract

An embodiment of the present application provides a double-ended data transmission circuit and a memory. The double-ended data transmission line includes: a first global data line and a second global data line that are mutually differential data transmission lines; a first local data line that is mutually differential data transmission lines The data line and the second local data line; the conversion module, connected between the external data line, the first global data line and the second global data line, is used to control the external data line and the first global data line according to the first control signal Data transmission between; enabling control module, used to output the third control signal; writing module, connected between the first local data line, the second local data line, the first global data line and the second global data line , based on the third control signal, it is judged that the data in the first global data line is transmitted to the first local data line and the data in the second global data line is transmitted to the second local data line; the present application aims to reduce memory power consumption and improve the reliability of data storage.

Description

technical field [0001] The present application relates to the field of semiconductor circuit design, in particular to a double-terminal data transmission circuit and memory. Background technique [0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of storage units is getting higher and higher; at the same time, various applications have higher and higher requirements on the performance, power consumption and reliability of DRAM. [0003] However, the existing memory still has room for improvement in terms of power consumption and reliability. It is urgent to design a memory that can reduce power consumption and improve storage reliability, and further improve the overall performance of the existing memory to face various applications. scene requirements. Co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4097
CPCG11C11/4097
Inventor 孙豳何军应战
Owner CHANGXIN MEMORY TECH INC