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46results about How to "Fix timing issues" patented technology

Data decompression device and method based on FPGA

The invention relates to a data decompression device and method based on an FPGA. The data decompression device comprises a physical layer interface module, a TCP/IP (Transmission Control Protocol/Internet Protocol) module, a sub-packaging module, a decompression module and an output module which are connected in sequence, the sub-packaging module is further directly connected with the output module, and the physical layer interface module is used for receiving network data, performing MAC layer analysis on the network data and then transmitting the network data to the TCP/IP module; the TCP/IP module is used for performing TCP analysis on the network data to obtain application data; the subpackaging module is used for segmenting and combining the application data to obtain a ZIP data packet and uncompressed data; the decompression module is used for decompressing the ZIP data packet to obtain decompressed data; and the output module transmits the decompressed data and the uncompresseddata to a computer. Compared with the prior art, the data decompression based on the FPGA can effectively replace a software decompression method, the CPU occupancy rate is reduced, the data delay isreduced, the data throughput is improved, and the purpose of quickly and accurately decompressing the data is achieved.
Owner:上海仪电(集团)有限公司中央研究院

Computer power and power state signal generating circuit thereon

The invention relates to a computer power comprising a system voltage output end, a backup voltage output end and a power state signal generating circuit. The power state signal generating circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and an electronic switch, wherein one end of the first resistor is connected with the system voltage output end and the other end is grounded through a capacitor; a node between the first resistor and the capacitor is connected with the in-phase input end of the operational amplifier; one end of the second resistor is connected with the backup voltage output end and the other end is grounded through the third resistor; a node between the second resistor and the third resistor is connected with the inverted input end of the operational amplifier; the output end of the operational amplifier outputs a power state signal; one end of the fourth resistor is connected with the system voltage output end and the other end is connected to the output end of the operational amplifier and the first end of the electronic switch; the second end of the electronic switch is grounded; and the third end of the electronic switch receives power-on signals sent by a computer mainboard through the fifth resistor. The power supply can satisfy the requirement of power time sequence of the mainboard.
Owner:HONG FU JIN PRECISION IND (SHENZHEN) CO LTD +1

Time sequence optimization circuit and method, chip and electronic equipment

The embodiment of the invention discloses a time sequence optimization circuit and method, a chip and electronic equipment, the electronic equipment comprises the chip provided with the time sequence optimization circuit, the time sequence optimization circuit comprises a first register, a second register and a third register, and the third register is a duplicated register of the first register; the path distance between the first register and the second register is greater than that between the third register and the second register; when a time sequence report obtained by executing the time sequence analysis command indicates that time sequence violation exists in the first time sequence path, the second time sequence path is used for performing time sequence optimization processing; the path starting point of the first time sequence path is a first register, and the path end point is a second register; the path starting point of the second time sequence path is the third register, and the path end point is the second register. The time sequence optimization method comprises the following steps: executing a time sequence analysis command to obtain a time sequence report; and when the time sequence report indicates that the time sequence violation exists in the first time sequence path, performing time sequence optimization processing through the second time sequence path.
Owner:GUANGDONG OPPO MOBILE TELECOMM CORP LTD

Battery Management System with Power Control

ActiveCN102231553BAvoid problems with wrong control strategiesWith automatic power lock functionBatteries circuit arrangementsElectric powerElectricityOvervoltage
The invention discloses a battery management system (BMS) with a power supply control function. The battery management system comprises an assisted power supply, a BMS power supply control module and a BMS functional module, wherein the BMS power supply control module comprises a main switch connected with the assisted power supply and the BMS functional module, a voltage detection and protection module for detecting the voltage of the assisted power supply and outputting a signal to control the main switch, a logical switch for receiving signals from the assisted power supply and BMS functional module and outputting a control signal to the voltage detection and protection module and a key switch connected with the assisted power supply, the logical switch and the BMS functional module. By the adoption of the battery management system, power supply control functions that the overvoltage-undervoltage detection and detection is carried out on the BMS power supply, a self-locked power supply is actively controlled after electrification, system safe detection and data storage are completed before the system is powered when a power switch is turned off are achieved, thereby effectively improving the reliability of the battery management system.
Owner:陕西法士特松正电驱系统股份有限公司

CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and implementing method thereof

The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.
Owner:ALLWIN TELECOMM

Mobile charging system and controlling method thereof

The invention discloses a mobile charging system and a controlling method thereof. The mobile charging system comprises an energy storage battery and a battery management system, wherein the input end of the energy storage battery is connected to a recharging interface of equipment through a switch S1, the output end of the energy storage battery is connected to a charging interface of an automobile through a switch S2 and a switch S3, a DC/AC charging module is arranged between the switch S2 and the charging interface of the automobile, an auxiliary power supply is arranged between the switch S3 and the charging interface of the automobile, the battery management system is connected with a switch S4, a contact A of the switch S4 is connected to the recharging interface of the equipment, and a contact B of the switch S4 is connected to the output end of the auxiliary power supply, a mobile charging controller is arranged between the switch S3 and the auxiliary power supply, the mobile charging controller is connected with a switch S5 used for selecting operation states, and the mobile charging controller can be used for controlling the switches S1-S4 through the operation state of the switch S5. According to the mobile charging system and the controlling method thereof, standby loss of the system is reduced, over discharge of the battery is prevented, the service life of the battery is prolonged, and meanwhile the problem of time sequence in the process of automobile charging and equipment recharging can be solved.
Owner:XIAN TGOOD INTELLIGENT CHARGING TECH CO LTD +1

A rs coding system based on cmmb and its realization method

The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.
Owner:ALLWIN TELECOMM

Gated clock conversion method based on recursive multi-way tree

The invention discloses a gated clock conversion method based on a recursive multi-way tree. The gated clock conversion method comprises the following steps: 1, acquiring a multi-way tree hierarchicalstructure of a module; 2, searching a gated clock module name and a clock output port name of the gated clock module to obtain a gated clock signal chain table; 3, searching a signal name of the gated clock signal linked list, obtaining names and positions of a gated clock signal and a derivative clock, analyzing the grammar type of the row, and storing the grammar type as a solved gated clock linked list; 4, simplifying linked list node identification fields, reserving module names, and deleting linked list repetitive elements to obtain a modified position linked list; 5, according to the grammar type of the modified position linked list signal, constructing a new modified linked list from the new modified content and replacing the new modified linked list; and 6, removing logic AND operation between the gating enable and the clock, and adding logic AND operation of the upper-level gating signal and the current-level gating signal. Platform verification of large-scale digital logic containing a gated clock becomes possible, and the method can be widely applied to the technical field of integrated circuit design.
Owner:武汉凌久微电子有限公司

Oil path structure of embedded multifunctional two-way holding valve

The invention discloses an embedded multifunctional two-way holding valve oil way structure, and belongs to the technical field of hydraulic valves. A main valve rod is installed in the first valve element hole of the valve body in a matched mode. A left one-way valve element, a linkage valve rod and a right one-way valve element are sequentially installed in a second valve element hole of the valve body. The oil port P and the oil port T are communicated to the main valve rod; the oil port A is communicated with a left one-way valve core and a spring cavity thereof; the oil port B is communicated with a right one-way valve core and a spring cavity thereof; the oil port Pi and the oil port DR are communicated through a linkage valve rod; the other end of the oil duct I is communicated with the right end of the left one-way valve core and the left end of the linkage valve rod; and the other end of the oil duct II is communicated with the left end of the right one-way valve core and the right end of the linkage valve rod. The linkage valve rod has the function of linkage of the executing mechanism and the function of pressure selection, soft opening and soft braking of the executing mechanism are achieved, the impact of opening and closing of the executing mechanism is avoided, the operation stability of the executing mechanism is improved, and the operation comfort is improved.
Owner:徐州阿马凯液压技术有限公司

A kind of SDN multi-thread timing control method, system, device and readable storage medium

The present application discloses an SDN multi-thread timing control method, system, device and computer-readable storage medium, comprising: receiving a network element device IP binding request sent by a virtual router; judging an IP corresponding to the network element device IP binding request Whether the binding tag semaphore of the address is in the unbound state; if the binding tag semaphore is in the unbound state, the IP address is allocated to the network element device recorded in the IP binding request of the network element device to complete the binding; If the fixed marked semaphore is not in the unbound state, continue to judge whether the bound marked semaphore of the IP address is in the unbound state; this application adds a binding marked semaphore for the IP address in advance for processing the IP binding of the network element device. Determine the binding state of the IP address when requesting, and do not perform an incorrect binding operation when the binding flag semaphore is not in the unbound state, and perform the binding operation until the binding flag semaphore is in the unbound state to ensure that the network element equipment is in the unbound state. The IP binding request can be effectively executed, which solves the timing problem.
Owner:北京浪潮数据技术有限公司
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