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A time sequence path correction method

A timing and path technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as the inability to optimize timing targets, achieve the effect of optimizing timing paths and ensuring normal operation

Inactive Publication Date: 2021-04-16
北京华大九天科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the number of spare spare units is insufficient, or the spare spare unit cannot be found within the specified range, the timing target cannot be optimized

Method used

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Examples

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Embodiment Construction

[0029] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0030] figure 1 It is a flow chart of the modification method of the timing path according to the present invention, and the following will refer to figure 1 , the method for modifying the timing path of the present invention is described in detail.

[0031] First, in step 101, determine the paths and units that violate timing.

[0032] Preferably, a timing path with a timing problem is determined, a unit that needs timing adjustment is found, and the unit type and physical location on the chip are obtained.

[0033] In this embodiment, it is assumed that the chip design enters the post-mask late stage, and it is no longer allowed to change the physical layout of ...

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PUM

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Abstract

The invention discloses a time sequence path correction method. The method comprises the following steps: determining a path and a unit of time sequence violation; setting a search range and searching an exchangeable unit; exchanging the time sequence violation units and the exchangeable units, evaluating new time sequence values of the two time sequence paths, and adding the exchangeable units which do not violate the time sequence and weight values of the exchangeable units into a result set; and in the result set, selecting the exchangeable unit with the maximum weight value to be exchanged with the time sequence violation unit to generate a result path. According to the time sequence path correction method, on the premise that the chip design physical layout is not changed and the chip function behavior is not changed, the purpose of time sequence optimization is achieved through unit exchange, so that time sequence correction can be carried out in the post-mask stage in the design later stage, and the correctness of chip design is guaranteed.

Description

technical field [0001] The present invention relates to the technical field of electronic design automation (EDA), in particular to a method for modifying timing without changing layout unit swap. Background technique [0002] In digital integrated circuit design, in order to ensure that the chip can work normally and achieve the expected frequency, it is necessary to check whether the time when the clock signal and data signal arrive at the register synchronization unit meets the constraints of setup time and hold time. If timing violations are found, ECO modifications are required to adjust the timing paths. [0003] Buffer cell insertion, cell size change, and large net splitting are commonly used timing optimization methods. For a timing path with a timing violation, the delay of the timing path is increased or decreased by means of cell insertion or cell size change, so as to correct the timing violation problem. However, the premise of this timing optimization is tha...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3312
Inventor 杨晓东刘毅傅静静陈彬王宗源
Owner 北京华大九天科技股份有限公司
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