Gated clock conversion method based on recursive multi-way tree

Abstract

The invention discloses a gated clock conversion method based on a recursive multi-way tree. The gated clock conversion method comprises the following steps: 1, acquiring a multi-way tree hierarchicalstructure of a module; 2, searching a gated clock module name and a clock output port name of the gated clock module to obtain a gated clock signal chain table; 3, searching a signal name of the gated clock signal linked list, obtaining names and positions of a gated clock signal and a derivative clock, analyzing the grammar type of the row, and storing the grammar type as a solved gated clock linked list; 4, simplifying linked list node identification fields, reserving module names, and deleting linked list repetitive elements to obtain a modified position linked list; 5, according to the grammar type of the modified position linked list signal, constructing a new modified linked list from the new modified content and replacing the new modified linked list; and 6, removing logic AND operation between the gating enable and the clock, and adding logic AND operation of the upper-level gating signal and the current-level gating signal. Platform verification of large-scale digital logic containing a gated clock becomes possible, and the method can be widely applied to the technical field of integrated circuit design.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a gating clock conversion method based on a recursive multi-fork tree. Background technique [0002] The gated clock circuit is a low-power design in digital circuits. The clock output is only available when the gating is valid, and the output clock is turned off at other times. When the circuit function is turned off, the clock can be turned off to reduce the output of the flip-flop. The number of flips plays a role in reducing dynamic power consumption. In some large-scale digital integrated circuits, considering the convenience of digital module integration, gated clock circuits have been widely used, which has also created the traditional structure of such circuits. In a typical gated clock circuit, the gated signal passes through a latch and then undergoes logical AND operation with the input clock to output the required gated clock. [0003] The register...

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Problems solved by technology

[0003] The register-level description of some digital integrated circuits contains a gate-controlled clock circuit. Although this circuit can be used normally in the simulation or tape-out process, it will cause clock cycle constraint violations during the verification process of the digital logic platform due to the existence of the gate-controlled circuit. The problem caused the layout and routing tool to fail to realize the required circuit

In response to this problem, FPGA (Field Programmable Gate Array) suppliers have added gated clock conversion tools to their synthesis tools, hoping to convert the gated clock structure into a clock enable structure during the circuit mapping process after synthesis. However, the circuit Optimization is still suboptimal - this method is completely ineffective for large digital circuits with frequent gating clocks, and can even lead to increased tool flow time

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