33results about How to "Save internal resources" patented technology

The invention provides an FPGA-based method and system for preventing relay protection misoperation. A CPU periodically transmits protection starting / outlet data to an FPGA, and when the FPGA detects that the protection starting / outlet data is valid, a starting / outlet relay is controlled to act; when the FPGA detects that a protection outlet state signal is invalid, and after a timed non-continued set time, the FPGA detects that the protection starting / outlet data is valid, the starting / outlet relay is controlled to act; or when the data is invalid, and after the timed non-continued set time, the starting / outlet relay is controlled not to act. By virtue of the method and the system, the protection starting / outlet data accuracy and relay protection action reliability are improved; in addition, the protection starting and outlet signals are sent out directly through the FPGA, without through an outlet plug-in, so that multilayer data transfer is reduced, and speed, reliability and accuracy of relay protection are improved; and furthermore, the periodical judgment on the protection data is simple in logic, troublesome signal content analysis is omitted, and the FPGA internal resource is saved.

The invention relates to a real-time digital image enhancement method and system, belonging to the technical field of digital image processing. When processing a digital image, the grayscale image collected by an industrial camera is obtained and transmitted to a first data conversion module by a CameraLink input interface for processing. The serial-to-parallel conversion is then transmitted to the FPGA chip. The FPGA chip acts as the core processing unit and the main control unit to control the logic timing of the entire system, process the image, and then transmit the image data to the second data conversion module for further processing. After a serial-to-parallel conversion, the enhanced image is output through the CameraLink output interface. The present invention is mainly implemented by utilizing internal resources of the FPGA, and adopts a pipeline method for data processing, thereby improving the image processing speed, occupying less resources, and reducing the power consumption of the FPGA.

The invention relates to an on-track reconfigurable method based on anti-fuse FPGA (field programmable gate array) and SRAM (static random access memory) FPGA because the SRAM FPGA is likely to have single event upset on the track, but the anti-fuse FPGA has the advantages of less internal resource, high reliability and applicability to the on-track control. According to the method, the anti-fuse FPGA and the SRAM FPGA are combined to process the on-track reconfiguration, the anti-fuse FPGA is used for receiving the reconfiguration data uploaded by the ground so as to reconfigure the function of the SRAM FPGA, so that not only can the stability and reliability in work of the SRAM FPGA be guaranteed, but also the on-track updating and maintenance requirement of a spacecraft can be met.

The invention discloses a data processing system and a data processing method, comprising: the address and data multiplexing bus pins of the CPU processor are connected with the data bus pins of the data storage device, and the CPU processor controls the Bus pins, addresses and data multiplex bus pins to send control commands and address information; after receiving the control commands and address information, the converter converts them into control signals and address signals in the format of the data storage device and sends them to the data storage device ; The data storage device responds to the data operation performed by the CPU processor through the address and data multiplexing bus pins and the data bus pins of the data storage device according to the control signal and the address signal. Using the invention, the data operation speed of the CPU processor to the peripheral devices is not affected by the converter, and the data does not need to be processed by the converter during data operation, which saves the internal resources of the converter.

The invention provides a group call service processing method of a broadband cluster communication system. The method comprises that when a group call is established but a downlink data packet of the group call is not received, a gateway sends first group call data loss information including the group number and identification of the group call to a mobility management entity (MME); if response information back fed by the MME is not received, resources of the group call of the gateway are released; and if the response information back fed by the MME is received, whether to release the resources of the group call is determined according to the received the response information of the MME. According to the method, the group call is established, whether the gateway includes downlink data of the group call is monitored, signaling interaction with the MME and an SCC is made when there is not downlink data of the group call, whether the group call is normal is determined, and a resource release mechanism is triggered when the group call is abnormal; and thus, bandwidth resources and internal resources of logical network elements are saved effectively. The invention also relates to a group call service processing system of the broadband cluster communication system.

The invention provides a full view video cylindrical surface image storage method and a system. The method includes that pixel data is received by row and first in,first out (FIFO) is used for caching. Whether an FIFO is full of the caching pixel data or not is judged. If it is full, a row of pixel data is continuously read out from the FIFO and the cylindrical surface transformation is carried out. New coordinates are obtained by calculating each pixel and the pixel addresses of each pixel are calculated. Data after the transformation of the cylindrical surface is divided into a plurality of data sections, wherein, among the divided data sections, the pixel address in every data section is consecutive and the next data sections belong to different rows. BURST is formed by the pixel numbers in the data section, the BURST proruption length in the internal memory, the storage unit digit of the internal memory and the pixel address of the first pixel in the data sections. The composed BURST data is stored into the internal memory. The full view video cylindrical surface image storage method and the system achieve the transformation of the cylindrical surface of the video image as well as improve the bandwidth availability ratio.

The invention discloses a Nand Flash bad block management method and device and a memory. The bad block management method comprises the steps of establishing a random access memory RAM in an FPGA module with the same block number as a Nand Flash module, adopting an address of each RAM as a block address of each block in the Nand Flash module, then, storing a detected block state of the each block in the Nand Flash module into a RAM of the corresponding address so that corresponding writing and reading operation can be conducted according to the address of the each RAM and block state data stored in the RAM. According to the Nand Flash bad block management method and device and the memory, the address of the RAM is adopted as the block address of the each block in the Nand Flash module, and thus the space occupied by the RAM storage block address is saved; moreover, the RAM address needs to be shown with only one counter, thus the storage space of the FPGA module is not occupied, and the inner resource of the FPGA module is further saved.

The invention discloses a digital oscilloscope capable of configuring multiplex digital interpolating and digital filtering functions. The digital oscilloscope comprises a digital interpolating and filtering module realized by an FPGA (field programmable gate array), wherein, the digital interpolating and filtering module determines the current operation mode according to an interpolating / filtering gating signal, receives and stores input data, transfers the delayed data and filtering coefficients into a multiply and accumulate (MAC) calculating unit for calculation, and then transfers calculated results into a subsequent calculating unit; the subsequent calculating unit decides whether accumulation is required according to the current operation mode; when the operation mode is digital interpolating operation, the calculated results are directly taken as interpolation results to be output; and when the operation mode is digital filtering operation, digital filtering operation results are output after accumulation. The digital oscilloscope combines two signal processing modes such as digital interpolating and digital filtering into one by means of multiplexing mode configuration, thus effectively saving internal resources of the FPGA and being very economical and efficient.

The invention discloses a CORDIC algorithm-based capacitive micro-accelerometer signal detection device. The device comprises a capacitive micro-accelerometer sensor, a charge amplifying module, an analogue-to-digital converter, a field programmable gate array, a first digital-to-analogue converter, an analogue bandpass filter and a second digital-to-analogue converter, wherein the capacitive micro-accelerometer sensor, the charge amplifying module, the analogue-to-digital converter, the field programmable gate array, the first digital-to-analogue converter and the analogue bandpass filter are orderly connected; and the field programmable gate array is also connected with the second digital-to-analogue converter. The CORDIC algorithm-based capacitive micro-accelerometer signal detection device can regulate the phase, the frequency, the amplitude and the like of carrier signals in real time so as to achieve good flexibility, adopts high-frequency carrier modulation to suppress low-frequency noise, such as l / f noise and the like, adopts a digital modulation mode to overcome the defect that an analogue system is easy to be influenced by environmental factors, such as temperature and the like, and can control algorithm accuracy through iteration times and a data word size.

The invention provides a broadband digital receiver suited for pulse compression signals, which comprises a high-speed A / D sampling module, FPGA, DSP, a global clock module, a PLL configuration module, an AD sampling configuration module and the like, wherein the FPGA comprises an LVDS module, a CODE module, a multiphase wave filtering module and an FIR wave filter module. The broadband digital receiver digitally receives the broadband signals, divides the signals in the frequency domain in a channelizing way, reduces the data transfer rate, and makes use of the FPGA to realize the suited receiving of the pulse compression signals. The DSP is responsible for the calculation and dynamic loading of the weight coefficient of the suited wave filter. Compared with the analogy method, the receiver has the characteristics of better equipment quantity and reliability, and high sensitivity and dynamic loading.

The invention discloses a method for designing a DCMFK (Debiased Converted Measurement Kalman filter) based on an FPGA (Field Programmable Gate Array). Firstly, a system of the DCMFK based on the FPGA is designed. A gain matrix module comprises an average real covariance submodule and a gain matrix submodule; a state update module comprises a coordinate transformation submodule, an average real deviation submodule, an innovation submodule and a state update submodule; a trigonometric function module, a one-step prediction module, a prediction error covariance module, a filter error covariance module, the average real covariance submodule, the gain matrix submodule, the coordinate transformation submodule, the average real deviation submodule, the innovation submodule and the state update submodule respectively invoke floating adding, subtracting, multiplying and dividing operation modules. A hierarchical design is adopted in the method, modules at the bottom layer realize input by utilizing a VHDL (Very High Speed Integrated Circuit Hardware Description Language), and a schematic diagram input manner is adopted by the modules on the top layer; therefore, the method can improve the readability of codes, is easy to divide modules, and is convenient to simulate during designing.