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33results about How to "Save internal resources" patented technology

Digital oscilloscope capable of configuring multiplex digital interpolating and digital filtering functions

The invention discloses a digital oscilloscope capable of configuring multiplex digital interpolating and digital filtering functions. The digital oscilloscope comprises a digital interpolating and filtering module realized by an FPGA (field programmable gate array), wherein, the digital interpolating and filtering module determines the current operation mode according to an interpolating / filtering gating signal, receives and stores input data, transfers the delayed data and filtering coefficients into a multiply and accumulate (MAC) calculating unit for calculation, and then transfers calculated results into a subsequent calculating unit; the subsequent calculating unit decides whether accumulation is required according to the current operation mode; when the operation mode is digital interpolating operation, the calculated results are directly taken as interpolation results to be output; and when the operation mode is digital filtering operation, digital filtering operation results are output after accumulation. The digital oscilloscope combines two signal processing modes such as digital interpolating and digital filtering into one by means of multiplexing mode configuration, thus effectively saving internal resources of the FPGA and being very economical and efficient.
Owner:RIGOL

Method and apparatus for acquiring projected angle in image reconstruction

The present invention discloses a projection angle acquisition method in the image reconstruction and a projection angle acquisition device for the image reconstruction. The present invention measures the moving speed of a bulb tube in the preset speed position of the moving track of the bulb tube, determines the moving speed of each projection position according to the measured moving speed of the bulb tube and acquires the corresponding projection angle of each projection position. Compared with the prior time-triggered scanning process, the present invention increases the accuracy of the projection angle; compared with the prior position-triggered scanning process, the present invention not only increases the accuracy of the projection angle but also reduces the realization cost. In addition, the moving speed of the bulb tube is premeasured and stored so as not to redetermine the speed of the projection position in each scanning process under the condition that the moving speed of the bulb tube has no great change, thus saving the internal resources of the CT machine; or the measurement of each scanning period further ensures the accuracy of the moving speed of each projection position, thus ensuring the accuracy of the projection angle.
Owner:SIEMENS SHANGHAI MEDICAL EQUIP LTD

CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and implementing method thereof

The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.
Owner:ALLWIN TELECOMM

A low-energy consumption fingerprint identification method under a mobile phone screen

The invention discloses a low-energy-consumption fingerprint identification method under a mobile phone screen, which comprises the following steps: a mobile phone is in a dormant state and waits fora dormant wake-up event; the mobile phone is awakened and enters a fingerprint identification mode; the touch panel displays a fingerprint guide icon; after the touch panel receives the fingerprint pressing, the fingerprint guide icon is changed into pure color and the brightness is kept; the fingerprint identification module is awakened in a dormant state; after waking up, the mobile phone central controller sends an acquisition instruction to the fingerprint identification module, and the fingerprint identification module performs fingerprint image acquisition; after the collected image is interacted with the mobile phone center control, fingerprint recognition is carried out through a recognition algorithm, and a result is returned to the upper-layer application program. A good recognition environment is provided by utilizing the conditions of the mobile phone, so that the optical fingerprint sensor can carry out fingerprint recognition in any external environment; by combining theawakening mobile phone, the awakening fingerprint identification module and the mobile phone central control, the internal resources of the mobile phone can be effectively saved, and the limited endurance time of the mobile phone is ensured.
Owner:SHANGHAI FINGER TECH CO LTD

System and method for rapidly determining single phase earth fault

The invention discloses a system and method for rapidly determining a single phase earth fault. A structure of the system comprises a voltage transformer connected with electric signals, an isolation amplifier, a filtering rectifier, a hysteresis comparator, a monostable circuit capable of being repeatedly triggered and a microcontroller, wherein the microcontroller is connected with the hysteresis comparator and the monostable circuit capable of being repeatedly triggered. According to the system and method for rapidly determining the single phase earth fault, a characteristic of rapid responding and determining of hardware can be realized, and an advantage of flexible threshold value setting of software can be retained; during single phase earth fault determining operation, alternating current voltage signals are converted into a continuous pulse string via combination of a filtering rectification circuit and the hysteresis comparator; specifically the monostable circuit capable of being repeatedly triggered is adopted, and the pulse string is shaped into a signal pulse having a rising edge characteristic via which determining operation can be conducted via the microcontroller; via the method, a problem of threshold value jitter in a conventional hardware method can be effectively prevented, flexible threshold value setting can be realized via the microcontroller, strong universality can be realized, and high transferability is achieved.
Owner:WUHAN HAIO ELECTRIC

A rs coding system based on cmmb and its realization method

The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.
Owner:ALLWIN TELECOMM

Group call service processing method and system of a broadband trunking communication system

The invention provides a group call service processing method of a broadband cluster communication system. The method comprises that when a group call is established but a downlink data packet of the group call is not received, a gateway sends first group call data loss information including the group number and identification of the group call to a mobility management entity (MME); if response information back fed by the MME is not received, resources of the group call of the gateway are released; and if the response information back fed by the MME is received, whether to release the resources of the group call is determined according to the received the response information of the MME. According to the method, the group call is established, whether the gateway includes downlink data of the group call is monitored, signaling interaction with the MME and an SCC is made when there is not downlink data of the group call, whether the group call is normal is determined, and a resource release mechanism is triggered when the group call is abnormal; and thus, bandwidth resources and internal resources of logical network elements are saved effectively. The invention also relates to a group call service processing system of the broadband cluster communication system.
Owner:POTEVIO INFORMATION TECH CO LTD

A digital oscilloscope with configurable multiplexing digital interpolation and digital filtering functions

The invention discloses a digital oscilloscope capable of configuring multiplex digital interpolating and digital filtering functions. The digital oscilloscope comprises a digital interpolating and filtering module realized by an FPGA (field programmable gate array), wherein, the digital interpolating and filtering module determines the current operation mode according to an interpolating / filtering gating signal, receives and stores input data, transfers the delayed data and filtering coefficients into a multiply and accumulate (MAC) calculating unit for calculation, and then transfers calculated results into a subsequent calculating unit; the subsequent calculating unit decides whether accumulation is required according to the current operation mode; when the operation mode is digital interpolating operation, the calculated results are directly taken as interpolation results to be output; and when the operation mode is digital filtering operation, digital filtering operation results are output after accumulation. The digital oscilloscope combines two signal processing modes such as digital interpolating and digital filtering into one by means of multiplexing mode configuration, thus effectively saving internal resources of the FPGA and being very economical and efficient.
Owner:RIGOL

CORDIC algorithm-based capacitive micro-accelerometer signal detection device

InactiveCN101738495BOvercome the shortcomings of being susceptible to environmental factors such as temperatureSuppress low frequency noiseAcceleration measurementBandpass filteringAccelerometer
The invention discloses a CORDIC algorithm-based capacitive micro-accelerometer signal detection device. The device comprises a capacitive micro-accelerometer sensor, a charge amplifying module, an analogue-to-digital converter, a field programmable gate array, a first digital-to-analogue converter, an analogue bandpass filter and a second digital-to-analogue converter, wherein the capacitive micro-accelerometer sensor, the charge amplifying module, the analogue-to-digital converter, the field programmable gate array, the first digital-to-analogue converter and the analogue bandpass filter are orderly connected; and the field programmable gate array is also connected with the second digital-to-analogue converter. The CORDIC algorithm-based capacitive micro-accelerometer signal detection device can regulate the phase, the frequency, the amplitude and the like of carrier signals in real time so as to achieve good flexibility, adopts high-frequency carrier modulation to suppress low-frequency noise, such as l / f noise and the like, adopts a digital modulation mode to overcome the defect that an analogue system is easy to be influenced by environmental factors, such as temperature and the like, and can control algorithm accuracy through iteration times and a data word size.
Owner:ZHEJIANG UNIV

Method for designing DCMFK (Debiased Converted Measurement Kalman filter) based on FPGA (Field Programmable Gate Array)

The invention discloses a method for designing a DCMFK (Debiased Converted Measurement Kalman filter) based on an FPGA (Field Programmable Gate Array). Firstly, a system of the DCMFK based on the FPGA is designed. A gain matrix module comprises an average real covariance submodule and a gain matrix submodule; a state update module comprises a coordinate transformation submodule, an average real deviation submodule, an innovation submodule and a state update submodule; a trigonometric function module, a one-step prediction module, a prediction error covariance module, a filter error covariance module, the average real covariance submodule, the gain matrix submodule, the coordinate transformation submodule, the average real deviation submodule, the innovation submodule and the state update submodule respectively invoke floating adding, subtracting, multiplying and dividing operation modules. A hierarchical design is adopted in the method, modules at the bottom layer realize input by utilizing a VHDL (Very High Speed Integrated Circuit Hardware Description Language), and a schematic diagram input manner is adopted by the modules on the top layer; therefore, the method can improve the readability of codes, is easy to divide modules, and is convenient to simulate during designing.
Owner:NANJING UNIV OF SCI & TECH
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