33results about How to "Save internal resources" patented technology

The invention relates to a real-time digital image enhancement method and system, belonging to the technical field of digital image processing. When processing a digital image, the grayscale image collected by an industrial camera is obtained and transmitted to a first data conversion module by a CameraLink input interface for processing. The serial-to-parallel conversion is then transmitted to the FPGA chip. The FPGA chip acts as the core processing unit and the main control unit to control the logic timing of the entire system, process the image, and then transmit the image data to the second data conversion module for further processing. After a serial-to-parallel conversion, the enhanced image is output through the CameraLink output interface. The present invention is mainly implemented by utilizing internal resources of the FPGA, and adopts a pipeline method for data processing, thereby improving the image processing speed, occupying less resources, and reducing the power consumption of the FPGA.

The invention provides a full view video cylindrical surface image storage method and a system. The method includes that pixel data is received by row and first in,first out (FIFO) is used for caching. Whether an FIFO is full of the caching pixel data or not is judged. If it is full, a row of pixel data is continuously read out from the FIFO and the cylindrical surface transformation is carried out. New coordinates are obtained by calculating each pixel and the pixel addresses of each pixel are calculated. Data after the transformation of the cylindrical surface is divided into a plurality of data sections, wherein, among the divided data sections, the pixel address in every data section is consecutive and the next data sections belong to different rows. BURST is formed by the pixel numbers in the data section, the BURST proruption length in the internal memory, the storage unit digit of the internal memory and the pixel address of the first pixel in the data sections. The composed BURST data is stored into the internal memory. The full view video cylindrical surface image storage method and the system achieve the transformation of the cylindrical surface of the video image as well as improve the bandwidth availability ratio.

The invention discloses a Nand Flash bad block management method and device and a memory. The bad block management method comprises the steps of establishing a random access memory RAM in an FPGA module with the same block number as a Nand Flash module, adopting an address of each RAM as a block address of each block in the Nand Flash module, then, storing a detected block state of the each block in the Nand Flash module into a RAM of the corresponding address so that corresponding writing and reading operation can be conducted according to the address of the each RAM and block state data stored in the RAM. According to the Nand Flash bad block management method and device and the memory, the address of the RAM is adopted as the block address of the each block in the Nand Flash module, and thus the space occupied by the RAM storage block address is saved; moreover, the RAM address needs to be shown with only one counter, thus the storage space of the FPGA module is not occupied, and the inner resource of the FPGA module is further saved.

The invention discloses a CORDIC algorithm-based capacitive micro-accelerometer signal detection device. The device comprises a capacitive micro-accelerometer sensor, a charge amplifying module, an analogue-to-digital converter, a field programmable gate array, a first digital-to-analogue converter, an analogue bandpass filter and a second digital-to-analogue converter, wherein the capacitive micro-accelerometer sensor, the charge amplifying module, the analogue-to-digital converter, the field programmable gate array, the first digital-to-analogue converter and the analogue bandpass filter are orderly connected; and the field programmable gate array is also connected with the second digital-to-analogue converter. The CORDIC algorithm-based capacitive micro-accelerometer signal detection device can regulate the phase, the frequency, the amplitude and the like of carrier signals in real time so as to achieve good flexibility, adopts high-frequency carrier modulation to suppress low-frequency noise, such as l / f noise and the like, adopts a digital modulation mode to overcome the defect that an analogue system is easy to be influenced by environmental factors, such as temperature and the like, and can control algorithm accuracy through iteration times and a data word size.

The invention provides a broadband digital receiver suited for pulse compression signals, which comprises a high-speed A / D sampling module, FPGA, DSP, a global clock module, a PLL configuration module, an AD sampling configuration module and the like, wherein the FPGA comprises an LVDS module, a CODE module, a multiphase wave filtering module and an FIR wave filter module. The broadband digital receiver digitally receives the broadband signals, divides the signals in the frequency domain in a channelizing way, reduces the data transfer rate, and makes use of the FPGA to realize the suited receiving of the pulse compression signals. The DSP is responsible for the calculation and dynamic loading of the weight coefficient of the suited wave filter. Compared with the analogy method, the receiver has the characteristics of better equipment quantity and reliability, and high sensitivity and dynamic loading.