A rs coding system based on cmmb and its realization method

Abstract

The invention discloses a CMMB (China mobile multimedia broadcasting) based RS (reed-solomon) coding system and an implementing method thereof. The CMMB based RS coding system comprises an SDRAM (synchronous dynamic random access memory) controller, a byte interleaver, an internal memory and an RS coder, wherein the SDRAM controller is used for receiving information code streams and storing accessing check codes, the byte interleaver is used for subjecting accessing information codes and the check codes to byte interleaving, the internal memory is used for caching the accessing information codes and the check codes, and the RS coder is used for coding the information codes. The implementing method includes that the SDRAM controller receives the information code streams, the information codes are subjected to byte interleaving by the byte interleaver, the information codes interleaved are stored in the internal memory and are read and encoded and the like. By the CMMB based RS coding system and the implementing method thereof, internal resources of an FPGA (field programmable gate array) is effectively saved, and operation load is reduced, so that the problem about time sequence of the FPGA is solved, the low-end FPGA can be utilized for design, and normal work in complicated environment can be guaranteed.

Description

technical field [0001] The present invention relates to the communication field, in particular to a CMMB-based RS coding system and its realization method. Background technique [0002] Currently, RS encoders in the prior art are implemented using combinational logic, and high-end FPGAs are required. Because when using pure combinational logic circuits, RS coding requires a large number of combinational logic designs, and FPGA has relatively high timing requirements, and a large number of combinational logic circuits will cause timing problems, especially in complex environments. A high-end FPGA can alleviate the timing problems caused by a large number of combinational logic, but it will also be limited when processing clocks. Because if a sequential circuit is used, the coding rate of RS coding obtained from theoretical analysis is three times the data rate, that is, if the data rate is 60M-100M, then the coding rate should be close to 300M, which is difficult for FPGA Y...

AI Technical Summary

Problems solved by technology

Because when using pure combinational logic circuits, RS coding requires a lot of combinational logic design, and FPGA has relatively high timing requirements, and a large number of combinational logic circuits will cause timing problems, especially in complex environments

High-end FPGA can alleviate the timing problems caused by a large number of combinational logic, but it will also be limited when processing clocks

Because if a sequential circuit is used, the coding rate of RS coding obtained from theoretical analysis is three times the data rate, that is, if the data rate is 60M-100M, then the coding rate should be close to 300M, which is difficult for FPGA Yes, only the processing clock can be reduced, which not only affects the efficiency, but also multi-clock processing

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