7results about How to "Avoid risk of error" patented technology

The invention belongs to the field of chip design, and relates to a device and method for automatically checking clock interaction path asynchronous constraint rationality, and the device comprises an information generation module, a source synchronization degree score calculation module, a mutual exclusion degree score calculation module and a report generation module, and generates a clock interaction report required by a subsequent process based on a sign-off session. Extracting a clock pair which has signal interaction and is set to be not subjected to time sequence check, and forming a to-be-verified clock list L1; performing source synchronization degree score calculation on the clock pairs in the to-be-verified clock list L1, and forming an accurate check list L2; and common logic unit mutual exclusion degree calculation is carried out on the clock pairs in the precision check list L2, and a final clock list L is formed. In a chip design period, on the basis of the design constraint file, the clock pairs which have clock interaction but are set as non-check time sequences are automatically verified, and the clock pairs with wrong setting risks are displayed, so that the chip failure risk is effectively reduced.

The utility model discloses a vertical and horizontal integrated flash tester in the field of flash tester, this flash tester includes frame, and the middle part of frame is equipped with the measuring station for placing workpiece, and the measuring station is connected with the frame through the bottom base and can rotate horizontally relative to the base, the left end of measuring station is equipped with light source end, and the light source end contains the bottom light source of horizontal setting, is used for projecting light to the measuring station, the right end of measuring station is equipped with first detection end, and first detection end contains the first camera lens of horizontal, the first mobile module of driving this lens horizontal movement, and first camera lens periphery is equipped with the first diaphragm of projecting light to the measuring station, the top of measuring station is equipped with second detection end, and second detection end contains the second camera lens of vertical, the second mobile module of driving this lens lifting movement, and second camera lens periphery is equipped with the second diaphragm of projecting light to the measuring station. This flash tester is compatible vertical and horizontal detection structure, and can complete horizontal and vertical direction detection once, simplifies the operation process, and significantly improves the detection efficiency.

The invention discloses a wood product design order splitting method, system and device, a medium and a product, and the method comprises the steps that original data of wood product design are acquired, and the original data comprise design drawings and material details; and verifying and supplementing the material details based on the design drawing to obtain updated details, and determining a production blanking list, a price list and plate coding information according to the updated details. The method can improve the efficiency of a designer to compile a material detail table, save the time for deepening engineers to repeatedly check drawings and extract split details, and reduce errors in the operation process.

The invention discloses a single-line transmission method, device and equipment and a computer readable storage medium, which are applied to the technical field of computers, and comprise the following steps: packaging internal bus parallel data into a parallel data message according to a register read-write message protocol, and converting the parallel data message into a serial bit stream; mapping each logic bit of the serial bit stream into a level signal of a corresponding duty ratio according to a duty ratio coding rule; the duty ratio coding rule is that a logic bit 0 represents that a single high level exists in a clock period, and the duty ratio of the single high level does not reach half, and a logic bit 1 represents that a plurality of discontinuous high levels exist in the clock period, and the duty ratios of the plurality of discontinuous high levels reach half; and controlling the level conversion of the single signal line through a switching circuit according to the level signal, and transmitting the coded bit stream to the slave device bit by bit. According to the invention, the problems of high PCB design difficulty, high cost, signal interference and data error risk caused by a large number of signal lines are solved.

The application belongs to the chip design field and relates to a device and a method for automatically checking the rationality of asynchronous constraints of a clock interaction path. The device comprises an information generation module, a source synchronization score calculation module, a mutual exclusion score calculation module and a report generation module. Based on a signature session, a clock interaction report required for a subsequent process is generated, a clock pair with signal interaction but set to not perform timing check is extracted to form a clock list L1 to be verified; source synchronization score calculation is performed on the clock pair in the clock list L1 to be verified, and an accurate check list L2 is formed; mutual exclusion calculation of a common logic unit is performed on the clock pair in the accurate check list L2, and a final clock list L is formed. During the chip design cycle, the design constraint file is designed based on the application, the clock pair with clock interaction but set to not perform timing check is automatically verified, and the clock pair with the risk of error setting is displayed, so that the chip failure risk is effectively reduced.

The invention provides a model training environment recovery method and device, equipment and a storage medium, and the method comprises the steps: determining the scene configuration information of current equipment, and determining a target writing protocol mode according to the scene configuration information; obtaining model training state data at the current moment, and executing an atomization write-in operation of the model training state data according to the target write-in protocol mode to obtain a check point file at the current moment; and when the training environment is in a recovery stage, executing multi-layer verification on the stored check point file to obtain a verification result, and recovering the training environment based on the verification result. According to the method and the device, the multi-layer verification is performed on the check point file, so that the self-healing capability after the system crashes is improved, the training environment can be automatically recovered according to the verification result, manual recovery is not needed, the recovery time is saved, and the labor cost increase and the error risk are avoided.

Embodiments of the present specification provide a data query method and device, the method comprising: parsing, from a target query statement to be executed, a plurality of data tables to be queried, filter conditions of data tables in the plurality of data tables, and association conditions between the data tables; generating a first relationship graph based on the parsing result, wherein the first relationship graph comprises nodes corresponding to the plurality of data tables respectively, and target connection edges between the nodes for representing the association conditions, the nodes comprising reading methods supported by the data tables corresponding to the nodes, and the nodes corresponding to the data tables associated with the filter conditions further comprising the filter conditions; selecting, from the first relationship graph, nodes comprising filter conditions satisfying reading methods as first target nodes, and analyzing first query dependency relationships between the first target nodes and first neighbor nodes connected to the first target nodes through target connection edges; and generating a logical execution plan of the target query statement based on the first query dependency relationships, for joint query of the plurality of data tables.