Time sequence optimization circuit and method, chip and electronic equipment

Abstract

The embodiment of the invention discloses a time sequence optimization circuit and method, a chip and electronic equipment, the electronic equipment comprises the chip provided with the time sequence optimization circuit, the time sequence optimization circuit comprises a first register, a second register and a third register, and the third register is a duplicated register of the first register; the path distance between the first register and the second register is greater than that between the third register and the second register; when a time sequence report obtained by executing the time sequence analysis command indicates that time sequence violation exists in the first time sequence path, the second time sequence path is used for performing time sequence optimization processing; the path starting point of the first time sequence path is a first register, and the path end point is a second register; the path starting point of the second time sequence path is the third register, and the path end point is the second register. The time sequence optimization method comprises the following steps: executing a time sequence analysis command to obtain a time sequence report; and when the time sequence report indicates that the time sequence violation exists in the first time sequence path, performing time sequence optimization processing through the second time sequence path.

Description

technical field [0001] The present invention relates to the technical field of integrated circuit design, in particular to a timing optimization circuit and method, a chip and an electronic device. Background technique [0002] As the scale of chip design becomes larger, the competition becomes more intense, the timing closure becomes more and more complicated, and the requirements for the back-end design of the chip become higher and higher. With the support of powerful Electronic Design Automation (EDA) tools, most of the timing problems can be solved automatically. However, when the chip design enters the Engineering Changing Order (ECO) stage, it is inevitable that some individuals will be left behind. The timing problem is not optimized by the tool. [0003] At present, for the remaining timing violations in the ECO stage, common optimization methods such as optimizing the data path, extending or shortening the clock tree, etc., the effect of timing optimization is not...

AI Technical Summary

Problems solved by technology

With the support of powerful Electronics Design Automation (EDA) tools, most of the timing problems can be solved automatically. However, when chip design enters the Engineering Change Order (ECO) stage, it is inevitable that some The timing problem is not optimized by the tool

[0003] At present, for the remaining timing violations in the ECO stage, common optimization methods such as optimizing the data path, extending or shortening the clock tree, etc., the effect of timing optimization is not ideal, which seriously affects the progress of the project and chip performance.

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