Time sequence error correction system and method

Abstract

The invention relates to a time sequence error correction system which comprises a data path, a clock path with adjustable delay, a serializing unit, a driving unit and a counting and judging unit, wherein the data path is used for receiving parallel data; the clock path with the adjustable delay is used for receiving a clock signal; the serializing unit is connected with the data path and the clock path with the adjustable delay and used for converting the parallel data into serial data; the driving unit is used for converting the serial data into a current signal or a voltage signal and outputting the signal; and the counting and judging unit is used for calculating the number of rising edges or falling edges of the serial data and sending a regulating signal for regulating the delay time of the clock signal to the clock path with the adjustable delay to control the time sequence of the serializing unit so as to ensure that the number of the rising edges or the falling edges is the same as a preset correct number, and the time sequence of the serializing unit reaches an optimal value. The invention also provides a time sequence error correction method. The method effectively solves the time sequence problem in a serializing process.

Description

technical field

[0001] The invention relates to an error correction system and method, in particular to a time sequence error correction system and method for a sending end in a high-speed serial data transmission system. Background technique

[0002] In a high-speed serial data transmission system, in the process of serializing parallel data, the sending end usually uses a half-speed clock to serialize parallel data, that is, the clock period is half of the data bit width. In the process of serialization, due to the increase of the data rate, the timing is easy to make mistakes, especially affected by changes in the process, power supply, temperature, etc., the timing problem is particularly prominent.

[0003] During the data serialization process, the delay deviation of the synchronous clock and data on their respective paths makes the timing of the clock and data unable to meet the requirements of data serialization, which eventually leads to increased serial data jitter...

Examples

Embodiment approach

[0022] see figure 2 A preferred embodiment of the timing error correction method of the present invention includes the following steps:

[0023] Step 1: Input a preset parallel data training code through the data path, and input a clock signal through the delay-adjustable clock path.

[0024] Step 2: The serialization unit converts the parallel data training code into serial data.

[0025] Step 3: The counting and judging unit calculates the number of rising or falling edges of the serial data within a set time, and sends an adjustment signal for controlling the delay time of the clock signal to the clock channel with adjustable delay.

[0026] Step 4: The counting and judging unit controls the delay of the clock signal from large to small or from small to large by adjusting the signal. When the delay of the clock signal relative to the data becomes smaller, the sampling time of the clock signal is advanced, and the timing is wrong. The number of rising or falling edges of ...

technical field

[0001] The invention relates to an error correction system and method, in particular to a time sequence error correction system and method for a sending end in a high-speed serial data transmission system. Background technique

[0002] In a high-speed serial data transmission system, in the process of serializing parallel data, the sending end usually uses a half-speed clock to serialize parallel data, that is, the clock period is half of the data bit width. In the process of serialization, due to the increase of the data rate, the timing is easy to make mistakes, especially affected by changes in the process, power supply, temperature, etc., the timing problem is particularly prominent.

[0003] During the data serialization process, the delay deviation of the synchronous clock and data on their respective paths makes the timing of the clock and data unable to meet the requirements of data serialization, which eventually leads to increased serial data jitter...

Examples

Embodiment approach

[0022] see figure 2 A preferred embodiment of the timing error correction method of the present invention includes the following steps:

[0023] Step 1: Input a preset parallel data training code through the data path, and input a clock signal through the delay-adjustable clock path.

[0024] Step 2: The serialization unit converts the parallel data training code into serial data.

[0025] Step 3: The counting and judging unit calculates the number of rising or falling edges of the serial data within a set time, and sends an adjustment signal for controlling the delay time of the clock signal to the clock channel with adjustable delay.

[0026] Step 4: The counting and judging unit controls the delay of the clock signal from large to small or from small to large by adjusting the signal. When the delay of the clock signal relative to the data becomes smaller, the sampling time of the clock signal is advanced, and the timing is wrong. The number of rising or falling edges of ...

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