A chip data processing method and system based on an AES-GCM

Abstract

The invention provides a chip data processing method and system based on an AES-GCM. The method comprises the steps that S1, initializing a chip; S2, performing AES encryption on the binary number '0'by using a key k to obtain a variable H, and calculating the integer power of the variable H; And S3, grouping the plaintext data based on an AES algorithm, carrying out point multiplication on eachgroup of plaintext data and the integer power of the corresponding variable H in a finite field, and finally obtaining the ICV value of the authentication tag. According to the invention, the delay ofdata processing is reduced, the operation speed of the chip is improved, the number of triggers is reduced, and the area of the chip is reduced.

Description

technical field [0001] The invention relates to the technical field of chip information security, in particular to an AES-GCM-based chip data processing method and system. Background technique [0002] The GCM algorithm (Galois / Counter Mode, using Counter mode for symmetric encryption, and with ICV message authentication code) can provide encryption and integrity verification of messages, and can provide integrity verification of additional authentication data. In practical applications In the scenario, some information does not need to be kept secret, but the receiver of the information needs to confirm its authenticity, such as source port, destination port, IV, etc. Therefore, this part of data needs to be added to the calculation of the ICV value (IntegrityCheck Value, authentication label) as additional authentication data. The AES algorithm (Advanced Encryption Standard, Advanced Data Encryption Standard) is a symmetric block cipher algorithm widely used in the field ...

AI Technical Summary

Problems solved by technology

[0005] In the existing technology, the H power operation is started after the chip is powered on and initialized. After the operation is completed, it is sent to the encryption and decryption engine for encryption or decryption operations. Since the H power budget requires a lot of AND and XOR logic, this stage requires many levels of combinatorial logic, and there will be timing issues

To solve the timing problem, it is necessary to increase the flip-flop, which leads to an increase in the delay of data processing and increases the chip area.

For example, if the data bit width is 200 bytes, 1600 flip-flops need to be added for each additional level of pipeline. The more flip-flops are added, the greater the area overhead and delay of the chip.

Images