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Control method and system for data transmission of data flow architecture neural network chip

A neural network and data transmission technology, applied in the control method and system field of data transmission, to achieve the effect of improving resource utilization efficiency, saving resources, and improving chip performance

Pending Publication Date: 2020-10-30
SHENZHEN CORERAIN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present invention provide a data flow architecture neural network chip data transmission control method and system to solve the timing problem caused by control signal fan-out on the neural network chip designed based on the data flow architecture, and improve chip performance

Method used

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  • Control method and system for data transmission of data flow architecture neural network chip
  • Control method and system for data transmission of data flow architecture neural network chip
  • Control method and system for data transmission of data flow architecture neural network chip

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Embodiment 1

[0056] figure 1 A schematic flowchart of a method for controlling data transmission of a data flow architecture neural network chip provided by an embodiment of the present invention is applicable to the scenario of transmitting data in a neural network chip based on a data flow architecture design. The method can be implemented by The data flow architecture is implemented by the control system of the data transmission of the neural network chip. In this embodiment, the neural network chip designed based on the data flow architecture is referred to as the data flow architecture neural network chip for short.

[0057] Such as figure 1 As shown, the data transmission control method of the data flow architecture neural network chip provided by the embodiment of the present invention includes:

[0058] S110. The first register receives the write control signal generated by the control module according to the data to be written.

[0059] Wherein, the first register refers to a r...

Embodiment 2

[0074] figure 2 It is a schematic flowchart of a method for controlling data transmission of a data flow architecture neural network chip provided by an embodiment of the present invention. This embodiment is an optional embodiment based on the above technical solution, and is applicable to the scenario of transmitting data in a neural network chip designed based on a data flow architecture. The method can be executed by the data transmission control system of the neural network chip with the data flow architecture. In this embodiment, the neural network chip designed based on the data flow architecture is referred to as the data flow architecture neural network chip for short.

[0075] Such as figure 2 As shown, the data transmission control method of the data flow architecture neural network chip provided by the embodiment of the present invention includes:

[0076] S210. The first register receives the write control signal generated by the control module according to t...

Embodiment 3

[0107] image 3 It is a schematic structural diagram of a control system for data transmission of a neural network chip with a data stream architecture provided by an embodiment of the present invention. This embodiment is applicable to the scenario of transmitting data in a neural network chip based on a data stream architecture design.

[0108] Such as image 3 As shown, the data transmission control system of the data flow architecture neural network chip provided in this embodiment may include a first register 310, a control module 320, a second register 330, a first on-chip storage block 340 and a second on-chip storage area Block 350, where:

[0109] The first register 310 is electrically connected to the control module 320, and the first register 310 is configured to receive a write control signal generated by the control module 320 according to the data to be written;

[0110] The first register 310 is electrically connected to the second register 330, and the first ...

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Abstract

The embodiment of the invention discloses a control method and system for data transmission of a data flow architecture neural network chip. The method comprises the steps that a first register receives a write control signal generated by a control module according to-be-written data; the first register transmits the write control signal to a second register; a first on-chip storage block receivesfirst write data sent by the first register based on the write control signal; and a second on-chip storage block receives second write data sent by a second register based on the write control signal. According to the embodiment of the invention, the time sequence problem caused by control signal fan-out on the neural network chip based on data flow architecture design is solved, and the chip performance is improved.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of neural networks, and in particular to a method and system for controlling data transmission of a neural network chip with a data flow architecture. Background technique [0002] With the development of neural network technology, the traditional convolutional neural network chip developed based on the instruction set architecture can no longer meet the growing demand for computing power. Currently, the convolutional neural network chip developed based on the data flow architecture with high computing power and low latency performance Network chips have been paid more and more attention. [0003] The on-chip storage unit of the convolutional neural network chip developed based on the data flow architecture is composed of multiple on-chip storage blocks, which are used to store a large amount of data required for convolutional neural network calculations. In order to improve the co...

Claims

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Application Information

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IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/045Y02D10/00
Inventor 蔡权雄李远超牛昕宇
Owner SHENZHEN CORERAIN TECH CO LTD
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