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Memory-efficient hardware cryptographic engine

A hardware encryption and memory technology, applied in encryption devices with shift registers/memory, instruments, internal/peripheral computer component protection, etc., can solve the problems of large area and complex integrated circuit occupation, and achieve less memory and less occupation. The effect of less space

Pending Publication Date: 2021-03-16
NORDIC SEMICONDUCTOR
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, known implementations are often complex and occupy a relatively large area on an integrated circuit

Method used

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  • Memory-efficient hardware cryptographic engine
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Embodiment Construction

[0054] Figure 4 A wireless temperature sensor 1 is shown containing an integrated radio chip 2 , a battery 3 and a thermometer 4 . The temperature sensor 1 also contains other components, such as PCB, oscillator, capacitors, resistors, etc., which are omitted here for simplicity. The radio chip 2 includes a processor 5, memory 6 (which may include volatile and non-volatile memory types), an LTE Cat-M1 (LTE-M) radio 7, a hardware SNOW-3G cryptographic engine 8 (embodied as described above A disclosed hardware encryption engine) and an input / output peripheral 9 such as a USB interface. Of course, the radio chip may have other integrated peripherals and components. Processor 5 , memory 6 and peripherals 7 , 8 , 9 are connected to a memory bus 10 . The memory bus 10 can be an Arm TM AMBA bus system, including one or more Advanced High Performance Bus (AHB) and Advanced Peripheral Bus (APB). Memory bus 10 supports direct memory access (DMA) to memory 6 . The temperature sen...

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Abstract

A hardware cryptographic engine (8) comprises a direct-memory-access (DMA) input module (13) for receiving input data over a memory bus, and a cryptographic module (15). The cryptographic module (15)comprises an input register (20) having an input-register length, and circuitry (22) configured to perform a cryptographic operation on data in the input register (20). The hardware cryptographic engine (8) further comprises an input-alignment buffer (16) having a length that is less than twice said input-register length, and alignment circuitry (23) for performing an alignment operation on inputdata in the input-alignment buffer(16). The hardware cryptographic engine (8) is configured to pass input data, received by the DMA input module (13), from the memory bus (10) to the input register (20) of the cryptographic module (15) after buffering an amount of input data no greater than the length of the input-alignment buffer (16).

Description

Background technique [0001] The invention relates to a hardware encryption engine. [0002] Communication and storage systems often encrypt data to prevent unauthorized third parties from being able to access unencrypted data. A cipher is an algorithm that manipulates a "plaintext" message to produce an encrypted "ciphertext" message that is incomprehensible to unauthorized third parties but convertible back to plaintext data by an authorized user. This is usually accomplished by using a secret key known only to authorized participants. In symmetric ciphers, the same key is used for both encryption and decryption, while asymmetric ciphers use a public key for encryption and an associated private key for decryption. A large number of cryptographic algorithms and associated encryption schemes are known in the art. In addition to encryption and decryption operations, cryptographic algorithms may also be used within other cryptographic operations such as message authentication ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/72G06F21/74
CPCG06F21/72G06F21/74G06F13/28H04L9/06H04L2209/12
Inventor 马可·温布拉德马克库·瓦哈泰尼詹姆斯·尼瓦拉马蒂·蒂凯宁汉努·塔尔维蒂
Owner NORDIC SEMICONDUCTOR
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