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Data decompression device and method based on FPGA

A data decompression and data technology, applied in the direction of transmission modification based on link quality, digital transmission system, electrical components, etc., can solve the problem of inability to realize dynamic memory allocation storage matching code table, complex matching code table storage format, matching decoding cycle Matching time and other issues, to improve the accuracy of parsing, avoid excessive judgment conditions, and improve the speed of matching decoding

Active Publication Date: 2019-12-27
上海仪电(集团)有限公司中央研究院
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The rapid development of the current FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) chip has greatly improved its capacity and data processing speed, so the hardware function of the FPGA can be used to achieve the purpose of fast decompression of data. In technology, Haffman coding is usually used to re-express characters for data compression. However, due to the complex storage format of the matching code table, the hardware cannot realize dynamic memory allocation and storage of the matching code table. In addition, the length of Haffman coding does not exceed 15, and the frequency of occurrence is high. Short character codes and long character codes with low occurrence frequency. In the process of hardware decoding, there will be problems that the matching decoding of indefinite number of codes cannot be realized and the cycle matching time is too long. When the state jumps to the matching decoding results , the traditional method of privileged encoding is used to perform bitwise operations on the matching decoding results in turn, which will generate complex hardware circuits and cause timing problems caused by too many state jump conditions

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  • Data decompression device and method based on FPGA

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Embodiment Construction

[0056] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0057] Such as figure 1 Shown, a kind of data decompression device based on FPGA, comprises the physical layer interface module 1, TCP / IP module 2, subpackage group module 3, decompression module 4 and output module 5 connected successively, subpacket group module module 3 also Directly connected to the output module 5, the output module 5 is connected to the computer, wherein the output module 5 includes a DMA unit and a PCIe interface unit, specifically, the physical layer interface module 1 is connected to the network to receive network data, and perform MAC on the network data After layer analysis, it is transmitted to TCP / IP module 2;

[0058] TCP / IP module 2 performs TCP analysis on network data to obtain application data;

[0059] The subpackage module 3 then divides and combines the application data to obtain ZIP packets and uncompr...

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Abstract

The invention relates to a data decompression device and method based on an FPGA. The data decompression device comprises a physical layer interface module, a TCP / IP (Transmission Control Protocol / Internet Protocol) module, a sub-packaging module, a decompression module and an output module which are connected in sequence, the sub-packaging module is further directly connected with the output module, and the physical layer interface module is used for receiving network data, performing MAC layer analysis on the network data and then transmitting the network data to the TCP / IP module; the TCP / IP module is used for performing TCP analysis on the network data to obtain application data; the subpackaging module is used for segmenting and combining the application data to obtain a ZIP data packet and uncompressed data; the decompression module is used for decompressing the ZIP data packet to obtain decompressed data; and the output module transmits the decompressed data and the uncompresseddata to a computer. Compared with the prior art, the data decompression based on the FPGA can effectively replace a software decompression method, the CPU occupancy rate is reduced, the data delay isreduced, the data throughput is improved, and the purpose of quickly and accurately decompressing the data is achieved.

Description

technical field [0001] The invention relates to the field of software technology, in particular to an FPGA-based data decompression device and method. Background technique [0002] With the rapid development of information technology, computer networks have spread across every corner of daily life. In the process of using computer networks, there are massive amounts of data that need to be interacted with, which increases the requirements for data transmission and storage. Usually the compressed data will occupy much smaller storage space than the original data, and it will also occupy less bandwidth and reduce the transmission traffic of the server during the transmission process, so as to perform fast transmission. Therefore, it is necessary to compress the data for transmission or storage, and then decompress the data when it is needed. [0003] Most of the existing technologies directly use software to decompress data, but when the software decompresses large data, it w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00H04L29/06H04L29/08
CPCH04L69/161H04L69/04H04L69/22H04L69/322H04L67/06H04L1/0016H04L1/0061H04L67/568
Inventor 左佳赵中瑞
Owner 上海仪电(集团)有限公司中央研究院
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