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Automatic data layout method and device for heterogeneous fusion many-core architecture

A technology of automatic layout and data, applied in the computer field

Pending Publication Date: 2021-06-11
JIANGNAN INST OF COMPUTING TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to provide a data automatic layout method and device for heterogeneous fusion many-core architecture, the data automatic layout method and device for heterogeneous fusion many-core For example, the problem of manually adjusting the tile value to control the layout of key data does not require manual intervention by the user to achieve automatic layout of the data

Method used

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  • Automatic data layout method and device for heterogeneous fusion many-core architecture
  • Automatic data layout method and device for heterogeneous fusion many-core architecture
  • Automatic data layout method and device for heterogeneous fusion many-core architecture

Examples

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Embodiment

[0025] Embodiment: A data automatic layout device for heterogeneous fusion many-core architecture, including the following components:

[0026] The static analysis component configured on the compiler is used to collect all array accesses in the acceleration area and analyze its data access form. If the access form of all access points of the array satisfies A[a*i+b], where A is the array name, a and b are constants, and i is a parallel loop variable, then the array belongs to the key data that needs to be arranged in the on-chip cache, and can be distributed and laid out in the on-chip cache;

[0027] The static analysis component is a functional module of the static analysis of the compiler. It mainly analyzes the array variables accessed in the acceleration area. First, it collects all array accesses in the acceleration area and analyzes its data access forms. If all access points access The forms all satisfy the form of A[a*i+b] (A is the array name, a and b are constants,...

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Abstract

The invention discloses an automatic data layout method and device for a heterogeneous fusion many-core architecture. The method comprises the following steps: S1, a compiler determines an array which can be distributed and arranged to a cache on a computing core array chip through a static analysis part; s2, the compiler uses a code plug-in assembly to register related information of the array arranged to the on-chip cache; s3, the compiler obtains an optimal tile value through calculation according to the registration information and the loop index variable obtained by the dynamic analysis part and the relational expression, and updates the obtained optimal tile value to an internal database; s4, the compiler performs block division on the circulation again according to the optimal tile value, and regenerates an executable many-core acceleration target code; and S5, executing the executable many-core acceleration target code generated by compiling to enable the data layout to be optimal. The problem that a user needs to manually adjust tile values of different scales of examples of the same program to control key data layout is solved, manual intervention of the user is not needed, and automatic data layout is achieved.

Description

technical field [0001] The invention relates to a data automatic layout method and device for a heterogeneous fusion many-core architecture, belonging to the technical field of computers. Background technique [0002] A processor with a heterogeneous fusion architecture is usually composed of a control core unit and a computing core array. The control core is responsible for program initialization, I / O, communication, and task assignment of the computing core array. Work faster. Each computing core is usually equipped with an on-chip cache SPM, which has fast access speed and low latency. The key data of the accelerated core segment can only be laid out to the on-chip cache through DMA (Direct Memory Access) to achieve the best acceleration effect. [0003] Under the heterogeneous many-core processor architecture, the capacity of the on-chip high-speed local storage space is limited, and the data scale of the actual application subject will vary with the data to be solved. ...

Claims

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Application Information

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IPC IPC(8): G06F15/177G06F8/30G06F8/41
CPCG06F15/177G06F8/37G06F8/41G06F8/443
Inventor 张立博顾龙姜小成孙俊尤洪涛毛兴权
Owner JIANGNAN INST OF COMPUTING TECH
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