Manufacturing method of solid state disk and solid state disk
A manufacturing method and technology for solid-state hard disks, which are applied in the input/output process of data processing, instruments, electrical digital data processing, etc. The effect of increasing storage capacity, improving data transmission speed, improving data processing efficiency and service life
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Embodiment 1
[0030] see figure 1 and figure 2 , the manufacturing method of the solid state hard disk 100 of the embodiment of the present invention comprises the steps:
[0031] S1: provide an SSD controller 10 and the first NAND FLASH chip 20 connected to the SSD controller 10, the number of data channels of the SSD controller 10 is at least 8;
[0032] S2: provide a preprocessed cache module 30 and connect it to the SSD controller 10, the cache module 30 is composed of at least two different cache units 31;
[0033] S3: Determine the data size of the data transmitted by the cache module 30 to the first NAND FLASH chip 20, and classify the data with a data size smaller than the preset size as the first type of data, and classify the data with the data size larger than the preset size as the second type of data class data; and
[0034] S4: Transmitting the first type of data and the second type of data to different locations in the first NAND FLASH chip 20 for storage.
[0035] In th...
Embodiment 2
[0044] Further, see figure 1 and image 3 , the cache module 30 at least includes a second NAND FLASH chip and a DRAM chip arranged in parallel with the second NAND FLASH chip, and step S1 includes steps:
[0045] S11: converting the TLC particles in the second NAND FLASH chip into SLC particles through a conversion algorithm;
[0046] S12: Select a preset number of data channels from the SSD controller 10 to connect to the second NAND FLASH chip; and
[0047] S13: providing at least two DRAM chips arranged in parallel and connecting them to the SSD controller 10, wherein the bus of the DRAM chips is at least 16 bits.
[0048] In the embodiment of the present invention, the cache module 30 is composed of a preprocessed second NAND FLASH chip and a DRAM chip arranged in parallel therewith. In other embodiments, the cache module 30 may also be composed of at least two other cache units 31 , which is not specifically limited here.
[0049] Specifically, the preprocessing for ...
Embodiment 3
[0062] Further, see figure 1 and Figure 4 , step S11 includes the steps of:
[0063] S111 : Discard two bits among the three bits of the TLC particles in the second NAND FLASH chip, so that the TLC particles retain only one bit and transform into SLC particles.
[0064] Specifically, two bits in the three bits of the TLC particles in the second NAND FLASH chip are discarded, wherein the process of discarding the bits is the above-mentioned conversion algorithm, and the discarded bits can be any two bits of deleting or shielding the TLC particles , or invalidate any two bits in the TLC granules, so that the original TLC granules can be converted from the original 3-bit data storage to only 1-bit data storage, so that the TLC granules only retain one bit and are converted into SLC granules. The method is relatively simple , the implementation effect is better.
[0065] In one embodiment, if any two bits of TLC particles are deleted; in another embodiment, if any two bits of ...
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