Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Integrated test board card, chip test system and chip test method

A technology of integrated testing and chip testing, which is applied in automated testing systems, electronic circuit testing, electrical measurement, etc., and can solve problems such as low testing efficiency

Pending Publication Date: 2021-08-06
SUZHOU HUAXING YUANCHUANG TECH CO LTD
View PDF9 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Based on this, it is necessary to provide an integrated test board, chip test system and chip test method for the problem of low test efficiency caused by repeated useless acquisition operations on the PC side

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Integrated test board card, chip test system and chip test method
  • Integrated test board card, chip test system and chip test method
  • Integrated test board card, chip test system and chip test method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] This embodiment provides an integrated test board 200 for testing the chip 300 to be tested. figure 1 The integrated test board 200 includes an interrupt generation module 210, a master module 220, and a functional test module 230.

[0041] Wherein, the interrupt generating module 210 is configured to generate a first interrupt trigger signal when the test command is received by the test terminal 100;

[0042] The master module 220 connects the interrupt generating module 210, in response to the first interrupt trigger signal, acquiring test parameter information corresponding to the test command, and configures the function test module 230 based on the test parameter information To test the function test module 230 for testing the standby chip 300, the test parameter information is stored in advance in the main control module;

[0043] The master module 220 is further configured to generate a response command after the function test module 230 is finished, and transmit the...

Embodiment 2

[0054] This embodiment provides a chip test system for testing the chip 300 to test, referring to figure 1 The chip test system includes a test terminal 100 and an integrated test board 200 provided by one embodiment, the test terminal 100 for generating a test instruction and transmitting the test instruction to the integrated test board 200, and When the second interrupt trigger signal is received, the test result is obtained.

[0055] Through the above chip test system, during the entire process of the test, the test terminal 100 only needs to issue a test instruction and after the test is triggered by the second interrupt trigger signal, replacing the traditional timing acquisition test data. In the way, avoid repeated unwanted acquisition operations, and the configuration test parameter information is directly from the integrated test board 200 to obtain the corresponding test parameter information according to the test instruction according to the test instruction, and does ...

Embodiment 3

[0060] This embodiment provides a chip test method, applied to integrated test board 200, reference image 3 The chip test method includes the following steps:

[0061] Step S200, receive the test instruction emitted by the test terminal 100 and generate a first interrupt trigger signal;

[0062] In response to the first interrupt trigger signal, the test parameter information corresponding to the test command is acquired, and the function test module 230 is configured according to the test parameter information to enable the function test module 230 to be tested. 300 carry out testing;

[0063] Step S600, generate a response command after the test is completed, and generate a second interrupt trigger signal;

[0064] In step S800, the second interrupt trigger signal is transmitted to the test terminal 100 to inform the test terminal 100 to acquire test results.

[0065] Through the above chip test method, during the entire process of test, the test terminal 100 only needs to issue...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the technical field of chip testing, and particularly discloses an integrated test board card, a system and a test method. The device comprises an interrupt generation module, a main control module and a function test module, wherein the interrupt generation module is used for generating a first interrupt trigger signal when receiving a test instruction sent by a test terminal; the main control module responds to the first interrupt trigger signal, obtains test parameter information corresponding to the test instruction, and configures a function test module according to the test parameter information, so that the function test module tests the to-be-tested chip; the main control module is also used for generating a response instruction after the test of the function test module is finished, and sending the response instruction to the interrupt generation module; and the interrupt generation module is also used for generating a second interrupt trigger signal when receiving the response instruction, and sending the second interrupt trigger signal to the test terminal so as to notify the test terminal to obtain a test result. The integrated test board card saves a lot of resources of the test terminal, and is beneficial to realizing efficient and stable test.

Description

Technical field [0001] The present invention relates to the field of chip testing, and in particular, to an integrated test board, a chip test system, and a chip test method. Background technique [0002] IC test equipment is often referred to as ATE (Automatic Test Equipment, Automated Test Equipment), which is generally collected by a large number of testers, controlled by computer, and implements various chips tests. [0003] Each ATE device often includes a plurality of test boards. Before testing, the PC side needs to configure all the test board parameters, then initiate functional testing, during the test, the PC terminal will generally get the test board. Test Data. However, due to the time difference between the PC end acquisition test data and the test board completion test generated test data, it causes a duplicate unwanted acquisition operation in the PC side, and the PC side is often connected to a large number of test boards, and the repeated useless operation will ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G01R31/28
CPCG01R31/2834G01R31/2851
Inventor 凌献忠田敏
Owner SUZHOU HUAXING YUANCHUANG TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com