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Method of enhancing layout pattern

A pattern and layout technology, applied in the field of enhanced layout patterns corrected by the optical proximity effect, can solve problems such as resist layer resist defects

Inactive Publication Date: 2021-08-20
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Transferring the layout pattern of the photomask to the resist layer on the wafer can cause defects in the resist layer and is a major issue in semiconductor manufacturing

Method used

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  • Method of enhancing layout pattern
  • Method of enhancing layout pattern
  • Method of enhancing layout pattern

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Embodiment Construction

[0161] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include the embodiment of forming the first feature and the second feature in direct contact, and may also include the embodiment of forming the first feature and the second feature on the first feature. An embodiment in which an additional feature is formed between a feature and a second feature such that the first feature and the second feature may not be in direct contact. Additionally, in various instances, the present disclosure may repeat element numbers and / or letters. This repetition is for simplicity and clarity and does not in itself s...

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Abstract

A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.

Description

technical field [0001] Some embodiments of the present disclosure relate to methods of enhancing layout patterns, in particular to methods of enhancing layout patterns based on vertex optical proximity correction. Background technique [0002] Photolithography transfers the layout pattern of the mask to the wafer so that etching, implantation or other steps only pre-define areas of the wafer. Transferring the layout pattern of the photomask to the resist layer on the wafer can cause defects in the resist layer and is a major issue in semiconductor manufacturing. An optical proximity correction (OPC) operation can be applied to the layout pattern of the reticle to reduce the defects of the reticle pattern. The optical proximity effect correction can modify the layout pattern of the photomask before the photolithography process to compensate the effect caused by the photolithography process. Efficient optical proximity correction operates on mask openings (such as holes, tre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/36G03F1/76G03F7/20
CPCG03F1/76G03F1/36G03F7/70441G03F7/70433G06F30/398
Inventor 游信胜
Owner TAIWAN SEMICON MFG CO LTD