Winograd convolution operation acceleration method and acceleration module

Abstract

The invention provides a Winograd convolution operation acceleration method and an acceleration module, and the method comprises the steps: splitting or filling an input matrix into a 4 * 4 input matrix and splitting or filling a convolution kernel matrix into a 3 * 3 convolution kernel matrix for the convolution operation of a non-3 * 3 shape through employing a convolution kernel splitting method based on a step length; respectively carrying out Winograd transformation on the 3 * 3 convolution kernel matrix and the 4 * 4 input matrix by using the convolution kernel transformation matrix G and the input matrix transformation matrix BT to obtain a transformed convolution kernel matrix U and a transformed input matrix V; performing weight splitting on elements u[xi]v in the transformed convolution kernel matrix U according to bit-level precision, and performing accumulation operation and shift operation to obtain a matrix Z; and performing Winograd transformation on the matrix Z to obtain an output matrix of convolution operation. According to the method, on-chip resources can be reasonably utilized, the calculation complexity is reduced, and convolution operations of most sizes can be compatible.

Description

technical field [0001] The invention relates to convolutional neural network calculations, in particular to a Winograd convolutional operation acceleration method and an acceleration module. Background technique [0002] Convolutional neural network (CNN) has been widely used in image classification and speech recognition. As the scale of applied data increases, the computational complexity of its network model is also increasing. In recent years, including automatic driving Many applications including CNN put forward higher real-time requirements. According to statistics, convolution calculation accounts for 99% of the total calculation volume of CNN. Therefore, accelerating the operation of convolution layer is the key to improving the calculation speed of convolutional neural network. [0003] High flexibility, low cost, and short design cycle make FPGA-based CNN accelerator designs more suitable for deployment in mobile devices. Depending on the type of convolution alg...

AI Technical Summary

Problems solved by technology

Aiming at the unbalanced design status of FPGA on-chip resource utilization, the inventor's research group once proposed a multiplication-free convolution acceleration scheme (MF-Conv), which can eliminate the multiplication operation of the convolution operation in the filter_loop. However, the hardware structure of this scheme It is determined by the size of the convolution kernel. For example, the 3×3 MF-Conv hardware acceleration unit cannot be compatible with the 5×5 convolution operation.

As can be seen from Table 2, the current design of CNN presents a trend of diversification in the size of the convolution kernel, so MF-Conv has certain limitations.

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