Loop delay compensation circuit and Sigma-Delta analog-to-digital converter

Abstract

The invention provides a loop delay compensation circuit and a Sigma Delta analog-to-digital converter, the working current of a differential input pair to an input clock signal is controlled by adjusting the input signal code values of DAC1-DAC4, the phase difference between a clock CKP1 and a clock CKP2 is 90 degrees, the phase difference between the clock CKP1 and a clock CKN1 is 180 degrees, the phase difference between the clock CKP1 and the clock CKP2 is 90 degrees, and the phase difference between the clock CKP1 and the clock CKN1 is 180 degrees. The four groups of clock signals are superposed on the resistor R1 and the resistor R2 at the same time to generate signals which have time delay in a clock period of the CKP1, and the delay time can be controlled by adjusting an input code value of DAC1 < 0: 3 >-DAC4 < 0: 3 >. According to the circuit, the delay time of the high-frequency sampling clock in one period can be adjusted by setting the input code values of the DAC1-DAC4 so as to be used for compensating loop delay, so that the problem of excessive loop delay is solved.

Description

technical field [0001] The invention belongs to the technical field of wideband continuous time Sigma Delta analog-to-digital conversion, in particular to a loop delay compensation circuit and a Sigma Delta analog-to-digital converter for high sampling frequency Sigma-Delta analog-to-digital converters. Background technique [0002] Nowadays, the analog-to-digital converter (ADC) is a necessary interface between the real world where analog signals are the mainstay and the powerful digital signal processing field, and is widely used. Different types of ADCs have their own advantages and disadvantages, and are suitable for different fields. Sigma-Delta ADC uses oversampling and noise shaping technology, not only can achieve high precision that cannot be achieved by other types, but also achieve a good compromise between speed and precision in some fields, reducing the requirements for front-end anti-aliasing filters. The basic structure is composed of two parts, Sigma-Delta mo...

AI Technical Summary

Problems solved by technology

[0004] In view of the problems existing in the prior art, the present invention provides a loop delay compensation circuit and a Sigma Delta analog-to-digital converter, which can arbitrarily adjust the delay time within one cycle of the high-frequency sampling clock in the Sigma Delta ADC, and is used to solve excessive loop delays. Latency issues, and improve the signal-to-noise ratio, allowing the system to achieve higher performance

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