Memory control system, address mapping method and address mapping device

An address mapping and memory technology, applied in the field of memory, can solve the problem that the file system cannot directly access or operate the memory chip

Active Publication Date: 2021-09-21
MAXIO TECH HANGZHOU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003]Because the data read and write of the memory chip of the solid-state hard disk depends on the physical characteristics, therefore, the existing file system cannot directly access or operate the memory chip

Method used

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  • Memory control system, address mapping method and address mapping device
  • Memory control system, address mapping method and address mapping device
  • Memory control system, address mapping method and address mapping device

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Embodiment Construction

[0028] The present invention is described below based on the examples, but the present invention is not limited to these examples. In the detailed description of the invention, some particular detail portions are described in detail. The description of these detail portions can also be fully understood in the art. In order to avoid obscuring the substances of the present invention, there is no detailed description. The drawings are not necessarily drawn to scale.

[0029] BRIEF DESCRIPTION OF THE DRAWININGGIES, block diagram illustrates a system, method, and a possible architecture of the embodiment of the present invention, function, and operation, flowchart, and block diagram on the flowchart, block, block, block or just a section. Code, the module, block, and code are executable instructions for implementing the specified logic functions. It should also be noted that the executable instructions that implement the predetermined logic function can be re-combined to generate new m...

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Abstract

The invention discloses a memory control system, an address mapping method and an address mapping device. A first-level mapping table and a second-level mapping table are stored in the memory. The address mapping method comprises the following steps: loading a first-level mapping table into a cache chip; when a host accesses the memory, obtaining a logic address of user data; searching a first-level mapping table in the cache chip by taking the logic address as an index to obtain an index address; and searching a second-level mapping table in the flash memory chip by taking the index address as an index to obtain the physical address of the user data, wherein the second-level mapping table is stored on a selected physical block of the memory, and the logic block address of the index address in the first-level mapping table is used for indicating the block address of the storage position of the second-level mapping table. According to the address mapping method, multi-level address mapping and block address compression are adopted to reduce the storage capacity requirement of the cache chip.

Description

Technical field [0001] The present application relates to memories, and more particularly to a control system and address mapping method and a device memory address mapping. Background technique [0002] Solid state drives (SSD, SOLID State Drive) are non-volatile data storage devices consisting of controllers and memory chip arrays. The storage medium of the solid state drive includes a flash chip or a DRAM chip. The interface of the solid-state drive can be compatible with a traditional hard disk as a storage medium, which has the advantages of small volume, light, low power, low, no mechanical noise, read / write speed than traditional hard drives, and is widely used for replacement. Traditional hard drives, such as laptops, industrial control, video surveillance, network monitoring, network terminals, navigation devices, and many other areas. [0003] Since the memory chip data reading and writing of the solid state drive depends on physical properties, the existing file syst...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0882G06F12/0897G06F12/06
CPCG06F12/0882G06F12/0897G06F12/0653Y02D10/00G06F2212/7201G06F12/0246
Inventor 骆小敏陈正亮蔡全盛栋梁褚世凯
Owner MAXIO TECH HANGZHOU LTD
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