A hierarchical soc test scheme based on ieee1149 and ieee1500 standards

Abstract

The invention discloses a hierarchical SoC testing scheme based on IEEE1149 and IEEE1500 standards, and relates to the field of SoC chip testing; wherein, the IEEE1500 standard protocol is used to independently test a single embedded kernel inside the SoC, and the embedded kernel and the system The core test interface is defined between to standardize the IP core test structure, so that the test multiplexing of the core is promoted through the core access mechanism; at the same time, the test and isolation of the core are effectively completed, and the switching between partition test blocks is achieved to achieve the purpose of a complete test of the SoC; By improving the peripheral circuits integrated by the IP core, the parallel synchronous test of the core and the outer core of the hierarchical SoC is realized, and the purpose of reducing the test time is finally achieved; it can provide a flexible and efficient design solution for large-scale SoC products.

Description

technical field [0001] The invention relates to the field of SoC chip testing, in particular to a hierarchical SoC testing scheme based on IEEE1149 and IEEE1500 standards. Background technique [0002] When integrated circuits (Integrated Circuit, referred to as IC) enter the era of VLSI, testability design is an important link in circuit and chip design. control and observability) hardware logic, which makes the chip easy to test and greatly saves the cost of chip testing. [0003] With the increase of integration and design complexity of System-on-a-chip (SoC for short), chip testing has encountered great challenges. On the one hand, IP multiplexing technology can speed up the SoC design process, improve system integration, and make a single chip more functional and more powerful; on the other hand, with the increase in the number of integrated IP cores on a single chip, SoC design complexity and The sharp increase in circuit scale has caused SoC testing to face huge cha...

AI Technical Summary

Problems solved by technology

Different suppliers will provide a variety of IP cores according to different test types and test requirements, but the detailed information inside the IP core is difficult to obtain due to intellectual property rights.

Usually, the data transfer speed between embedded cores is faster than the data transfer speed from chip pins to IP cores, so boundary scan alone cannot completely solve the testing problem of embedded cores in SoC

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