85 results about "System level testing" patented technology

A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.

Protection, measurement and control IEDs in a substation compute if switches they control may be operated safely, according to interlocking rules or physical principles as well as the dynamic topology of the substation. The IEDs have access to the substation electrical topology, to real-time information generated by other IEDs, and to the rules for interlocking. A standardized Substation Configuration Description (SCD) of the substation for which a Substation Automation system is intended, and a standardized description of the implemented device functions or capabilities of an individual IED are utilized. The substation topology is available from SCD file, real time information about the position of switches and line voltage/current can be obtained via an appropriate protocol, and the interlocking rules are available in script form. These features apply both to simulated and real devices, and increase system testing possibilities by supporting an efficient configuration of a simulation.

The disclosure is concerned with the testing of system level functionality involving several Protection, Control and Measurement (PCM) Intelligent Electronic Devices (IEDs) of a Substation Automation (SA) system for IEC 61850 compliant substations. An extensive testing of all conceivable control or protection functions/applications of an extended SA system comprising a large number of IEDs with a multitude of configurations is facilitated by simulating at least one of the IEDs in a testing device. Hence, only a limited number of IEDs are physically present as individual devices in a test environment, the behaviour of at least one further IED being simulated by a dedicated testing device with appropriate data processing means. The testing device sends network messages indicative of the behaviour of the simulated IED according to its communication and device configuration over a substation communication network to the physically present IED to be tested. The proper working of the configured IED functions, i.e. the expected correct action as triggered by the testing device, are then verified.

An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller coupled to a smart device in an enclosure, wherein the system controller comprises a memory comprising test logic and a processor. The enclosure comprises a plurality of components, wherein the processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic. The plurality of components comprises: (a) a robotic arm comprising a stylus affixed thereto; and (b) a platform comprising a device holder affixed thereto, wherein the smart device is inserted into the device holder; and (c) a wireless access point. The processor is further configured to: (a) control the smart device to activate wireless mode; (b) receive wireless signals from the wireless access point using the smart device; (c) retrieve wireless scan results from the smart device; and (d) analyze the wireless scan results.

A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of actions that comply with the set of constraints are used to generate an executable system-level test code.

Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.

A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.

The invention belongs to the field of system-level electromagnetic compatibility test and relates to a multi-machine mutual-interference test method for vehicle-mounted communication systems in the same car. The multi-machine mutual-interference test method for the vehicle-mounted communication systems in the same car builds the multi-machine mutual-interference test method for the same car to carry out multi-machine mutual-interference test for the same car on several communication systems with different communication frequency bands to inspect the interference situations of bottom noise, adjacent channel, co-frequency, harmonic wave and the like interference of a communication device in a power emitting state to the other communication systems in receiving states. The test method makes up the disadvantages that a system communication system compatibility test method does not have pertinence and is not good for operation and execution. The test method is correct in theory, quick and convenient to finish test, intuitive in result, capable of quantifying the signal decreasing situation of the communication system under the multi-machine mutual-interference state in the same car, and suitable for testing the compatibility between different types of vehicle communication systems.

A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. The scheduling methodology is based on an exploration of scheduling abilities in a hardware system and features a Hierarchical Scheduling Language for specifying transactions and their ordering. Through a grouping hierarchy, which may also be expressed in the form of an equivalent tree, the Hierarchical Scheduling Language combines the ability to stress related logical areas of the system with the possibility of applying high-level scheduling requests. A method for generating testcases based on request-files written in the Hierarchical Scheduling Language is also presented.

The invention discloses a system-level testability design optimization method based on PBI. The method includes: firstly, setting a weight vector based on a PBI method; calculating the lower limit ofthe penalty factor corresponding to each weight vector; and then iteratively searching an optimal influence factor vector based on a genetic algorithm, carrying out optimization by combining an objective function value and a PBI function value in a searching process to obtain a new population, and deleting a dominated solution in a final generation population to obtain a Pareto optimal solution set of the influence factor vector. With the adoption of the method, the convergence speed of the algorithm can be increased while the optimal solution is ensured to be obtained.

The invention discloses a top polarity testing and output value fault detection method. The method comprises the following steps: firstly, describing a top mounting matrix; secondly, solving top measurement angular velocity; thirdly, resolving satellite inertial angle speed and top output theoretical value by utilizing rotational angular velocity of the earth; fourthly, solving satellite inertialmeasurement angular velocity; and fifthly, locating a top in a fault state by utilizing multiple combinations of top headers. The method disclosed by the invention has the advantages that top polarityand output value can be conveniently and accurately tested, mutual fault monitoring among tops can be realized, a top whole satellite state testing process can be simplified, requirement on test equipment is lowered, workload is reduced, and the method disclosed by the invention not only can be applied to a top whole satellite testing process but also can be applied to a one machine level and system level testing process.

Method and system for automatically generating executable system-level tests. The method includes obtaining a system design including interrelation between components of the system design, actions the components are operable to perform, and constraints relating to the performance of the actions; receiving at least an initial action input to be tested; automatically generating a complete test scenario including: solving a logic layer CSP, including automatically scheduling actions and data paths of the test scenario, and assigning values to logic attributes of the actions and data, satisfying constraints relating to the logic layer, and solving a data layer CSP, satisfying constraints relating to data attributes taking into account the constraints relating to the logic layer; and generating the executable system-level test by assembling the initial action and the set of scheduled actions and data paths and the data attributes.

Devices and methods for DC and SLT (system level test) integration are disclosed. The DC circuit and the SLT circuit are integrated into the same device. Therefore, the DUT (device under testing) can precede the SLT before the FT (final test) when the DUT passes the DC.

The invention discloses an optical module system-level batch detection system and method, and the system comprises a module frame which is used for fixing optical modules; a jumper frame used for fixing an optical fiber jumper; and a monitoring software module used for acquiring state information of the tested optical module and the network equipment, generating a test result according to the testmode selected by the user, analyzing the test result and storing the test result in a database. The system is used for carrying out system-level batch detection on the optical modules. The operationis simple and the detection efficiency is high. Hot plug testing, power-on and power-off testing, connectivity testing, EEPROM information testing, digital diagnosis testing, flow testing and the likeof the module on network equipment such as a switch and the like can be realized. The system fills the gap of system-level testing between the optical module and network equipment such as a switch, and is widely applied to the aspects of factory delivery detection module quality of optical module manufacturers, switch factory detection hardware welding quality, switch factory detection module compatibility and the like.

The invention discloses a homemade computer based build in test system and method, which belong to the technical field of computer self-detection and achieve the effects that a build in test (BIT) function of a homemade computer is realized and the demands of a homemade computer platform on possession of fault detection and isolation capabilities and shortening of maintenance time are met. The technical scheme is that: the homemade computer based build in test system and method is provided; hardware involved in the system comprises a system-level testing module, a module-level testing module and a chip-level testing module; and software layers involved in the system include a hardware platform layer, a driver layer, a kernel layer, a support layer and an application layer. The homemade computer based build in test system and method adopts the self-detection system, performs self-detection on the homemade computer, and comprises power-on BIT, periodic BIT and maintenance BIT.

A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

The invention discloses a multipoint virtual data injection type intelligent transformer substation site debugging method. The multipoint virtual data injection type intelligent transformer substationsite debugging method comprises the following steps of (1) configuration analysis: determining a site test configuration of an intelligent transformer substation, a test data injection point quantityand a type; (2) data fitting: according to a sampling interval or a switch interval, virtualizing test data of all injection points; (3) sampling and switch loop debugging: debugging a sampling loopand a switch loop of the intelligent transformer substation; and (4) subsystem debugging: regionally debugging a secondary system of the intelligent transformer substation. The debugging method of theinvention is used to increase safety, reliability and economy of intelligent transformer substation construction engineering, a system acceptance period is effectively shortened, a guidance is provided for a lot of system-level tests in the further, and a good engineering application value is possessed.

The invention relates to a GRAPES system optimization method based on a parallel supercomputing grid cloud platform. The method comprises the steps that (S1) a test dataset is loaded, a system is run,and (S1.1) a system-level test, (S1.2) a communication-level test and (S1.3) a function-level test are performed separately, wherein in the (S1.3) function-level test, a called function is monitored,and running features of the function are acquired; (S2), test result analysis is performed according to an exported system feature file, wherein test result analysis comprises (S2.1) system test result analysis, (S2.2) MPI communication-level test result analysis and (S2.3) function-level test result analysis; and (S3) optimization processing is performed according to analysis results, wherein optimization processing comprises vectorization, load balancing and replacement of a function in a GRAPES_GFS by use of a library function. Through the method, optimization of Grapes on the parallel supercomputing grid platform is realized, and system running efficiency is improved.