32 results about "System level testing" patented technology

Methods, system, and computer program product are disclosed for enhanced system level testing of an AI hardware accelerator comprising Artificial Intelligence (AI) primitives. The system level testing provides uncompromised test coverage of the AI hardware accelerator while enabling efficient and effective testing performance. Enhanced test data generation, result prediction, and test execution are provided for system level testing of AI hardware accelerator including the AI primitives.

The invention relates to a verification and test integrated platform for a probe processor, and belongs to the technical field of processor verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional verification and test mode is difficult to consider the requirements of module-level verification and system-level test. The UVM verification system, the test system and the management module are integrated, and unified management of verification and test is achieved. The UVM verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test system is responsible for compiling test codes into machine codes and loading the machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test modes, so that the probe processor is suitable for different test scenes, the test efficiency is improved, and the environmental redundancy is reduced. According to the method, the reusability of the test case is improved, the test consistency is ensured, the resource utilization rate is optimized, the automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The application relates to the technical field of integrated circuit design and verification, in particular to a service test system for a texture block level, which generates a plurality of accurate controllable screen coordinates through a simulation geometry processing module and a simulation rasterization module and provides the screen coordinates to a texture processing module, so that the texture processing module can independently verify the logic of texture processing based on the generated screen coordinates, the reliability of the texture processing module does not need to be tested through system-level verification for service testing, the test requirement is lowered to the texture block level, thus the workload of system-level testing can be saved, the influence of problems of other modules on the texture processing module testing is avoided, the test difficulty is reduced, and the test efficiency and problem positioning accuracy of the texture block level service test are improved.

The invention discloses a system-level test strategy generation method and system based on a finished product test strategy. The method comprises the following steps: importing a finished product model and a corresponding signal development-oriented test strategy into a test platform; forming a finished product set A based on model selection, and forming a finished product level test strategy set T based on strategy selection; and screening related finished products of the tested system, screening all source and sink end names which are names of finished products at the other end of the non-current finished product according to source and sink information in an electrical interface in a finished product model, and forming a set B which is equal to a set B1 + a set B2. And according to the set B1 and the set B2, dividing the finished product level test strategy set T into a set C1 and a set C2, and performing system level test strategy conversion processing on the set C1. According to the method, the problem that a scheme from a current finished-product-level test strategy to a system-level test strategy is missing is solved, the system-level test strategy can be formed by comprehensively and quickly utilizing the existing finished-product-level test strategy, and convenience is provided for integrated testing of a complex system.

The test method, device, equipment and storage medium provided in the application first test each to-be-tested parameter of a preset number of DRAM samples through a system-level test machine and each standard parameter value in a high-temperature environment and a low-temperature environment, to obtain a corresponding first test result, then test each to-be-tested parameter of the DRAM sample with a failed first test result through a test machine and each target parameter value in a normal-temperature environment, to obtain a corresponding second test result. If the second test result is also failed, each to-be-tested parameter of the to-be-tested DRAM is tested through a test machine and each target parameter value in a normal-temperature environment, to realize that the normal-temperature environment replaces the high-temperature environment and the low-temperature environment to perform STL test on the to-be-tested DRAM sample, and test cost and test time are saved.

1. The name of the design product: multi-phase power controller system level test equipment. 2. The use of the design product: the design product is a test equipment for control board, electronic load board and signal detection board, used for simulating multi-phase power controller. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The invention discloses a test system for a remote diagnosis platform. The test system comprises an upper computer, a programmable power supply, a CAN network simulation board card and an entity ECU (Electronic Control Unit), such as a TBOX and a gateway, wherein the upper computer is used for locally running a remote diagnosis platform and a test program; the programmable power supply is used for supplying power to the entity ECU; the CAN network simulation board card is used for simulating a real vehicle network environment; the entity ECU is used as a test object, the TBOX and the gateway are connected through a plurality of diagnosis CAN network segments, and each diagnosis CAN network segment is provided with a plurality of virtual controller nodes. According to the invention, a rack system is established, a core controller related to remote diagnosis is subjected to physical carrying, other controllers are virtualized, and interaction is carried out by establishing a controlled simulation model, so that multi-dimensional system-level testing is carried out on the whole remote diagnosis platform; and full coverage of fault code reading and fault code simulation and reporting scenes of multiple controllers can be realized.

This invention relates to the field of CXL technology, specifically disclosing a latency testing method, apparatus, system, device, and medium for CXL units. By using an application message manager, messages are sent and received directly to the CXL unit through the corresponding computer fast interconnect interface module and the timestamps are recorded. The computer fast interconnect interface module includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. This enables direct hardware-based acquisition of message sending and receiving timestamps from the computer fast interconnect unit, avoiding link errors introduced in system-level testing and achieving direct measurement of the latency performance of the computer fast interconnect unit, thus realizing accurate latency performance testing of the computer fast interconnect unit.

The invention provides a temperature control method for a system-level test of a high-power-consumption chip. The method comprises the following steps: setting a test temperature of the high-power-consumption chip as a first test temperature through a test machine; at the first test temperature, the high-power-consumption chip starts to operate a first power consumption test case group; after one group of the first power consumption test cases is operated, the high-power-consumption chip sends a first temperature adjusting signal to the test machine; the test machine adjusts a test temperature to a second test temperature according to the first temperature adjustment signal, and sends a first temperature adjustment completion signal to the high power consumption chip; and after receiving the first temperature adjustment completion signal, the high-power-consumption chip starts to operate a second power consumption test case group at the second test temperature.

The application discloses an autonomous program control system level test method, and proposes a solution method for the correctness, effectiveness, safety and integrity of satellite active stage operation period satellite-rocket separation program control, autonomous flight program control, synchronous orbit stage operation period machine cutting program control, and emergency program control task verification. Based on satellite 1553B bus data simulation function and automatic test, satellite program control execution process is simulated and forwarded, satellite autonomous instruction sequence during program control execution is analyzed or intercepted, satellite program control process safety risk hidden danger is guaranteed, and effective verification of satellite autonomous program control function and comprehensive interpretation of instruction telemetry are realized.

This application discloses a testing method and laser equipment for a multi-mode master-slave control system, relating to the field of laser testing technology. It obtains structured text representing a hierarchical testing system, including a first text representing board-level characteristic testing rules and a second text representing system-level functional testing rules. Based on the first and second texts, board-level characteristic tests and system-level functional tests are performed on the master control board, slave control board, and beam combiner board, respectively, yielding board-level test results and system-level test results. Based on the board-level and system-level test results, a target text representing a comprehensive test report is generated. This achieves comprehensive testing and verification of the hardware foundation and system functional coordination of each board in the multi-mode master-slave control system, accurately identifying hardware defects and potential collaborative problems on each board. It provides a standardized solution to ensure the overall quality and reliability of the multi-mode master-slave control system, significantly improving the testing efficiency and reliability of the multi-mode master-slave control system.

The present invention discloses a chip testing method optimized based on deep learning, which relates to the technical field of chip testing, and includes: outputting the optimal power-on sequence through the Q-value update and the prioritized experience replay mechanism; extracting the electrical signal feature vectors of the pins through a convolutional neural network, adopting self-supervised learning, detecting abnormal connections between the pin signals through a contrast loss function, and judging whether there is a short circuit or an open circuit in the pins by calculating the signal feature distance to obtain the open-short circuit detection result of the chip; using a multi-layer perceptron for automatic tuning of configuration parameters to obtain optimized chip configuration parameters; using a recurrent neural network for system-level chip testing and verification to obtain system-level test results. The present invention achieves high efficiency, accuracy, and comprehensiveness that cannot be achieved by traditional methods in terms of power-on sequence optimization, open-short circuit detection, parameter tuning, and system-level testing, improves the efficiency and reliability of chip testing, and is applicable to the mass production and quality control of high-complexity chips.

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

The application provides a chip system-level test platform and a chip system-level test method, which comprises test board cards corresponding to each chip to be tested, a plurality of shared test modules and a field programmable gate array. The test board card comprises a plurality of unique test modules corresponding to the chip to be tested, each shared test module is connected with each test board card for shared use of each test board card. The field programmable gate array is connected with each shared test module and the chip to be tested, and is used for shared multiplexing control of each shared test module according to the requirement of each chip to be tested for each shared test module. In the scheme, each test board card is provided with a plurality of shared test modules in a shared manner, and is managed by the field programmable gate array, so that the size of the test board card is greatly reduced, the hardware resources are shared, more parallel tests of the test board cards can be realized on the limited test platform, and the test cost and the hardware resource overhead are greatly reduced.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

The invention discloses a complex system simulation method and device, electronic equipment and a storage medium, and the method comprises the steps: integrating a model of each subsystem of a current to-be-simulated complex system into a target simulation test platform, and constructing a system-level test model of the complex system; performing visual breakpoint debugging on the complex system in combination with the target simulation test platform and the source code compiler; simulating the system-level test model of the complex system through the target simulation test platform; in the simulation process, when simulation reaches a preset simulation stage, the enabling state of each model corresponding to the current simulation stage is set to be a first state, and the enabling states of the other models are set to be second states; wherein the models corresponding to the simulation stage are all models needing to be called in the simulation stage; and according to a simulation scheduling period of the current simulation stage determined according to the sensitivity of the current simulation stage to the simulation time, scheduling each model of which the current enabling state is the first state.

The invention discloses a voltage-regulated DRAM (Dynamic Random Access Memory) system-level test system and a screening method thereof. The system comprises a test mainboard, an external programmable current source module, an upper computer and a control panel. The test mainboard is integrated with a DRAM (Dynamic Random Access Memory) chip and a SoC (System on Chip), wherein the power supply input end of the DRAM chip and the PMIC are in an electrical open circuit state. The external current source module is independent of the SoC and the PMIC and provides multiple paths of independently adjusted power supply voltages for the DRAM chip. The upper computer is used for configuring a voltage change curve and triggering a test process, and the control panel is responsible for receiving an instruction of the upper computer and controlling the current source module to output a corresponding voltage value through a serial bus. Based on the system, the invention provides a screening method, different voltage conditions are applied to the DRAM chip, system-level testing is executed, and finally grading screening or reliability grade evaluation of the DRAM device is achieved. According to the invention, comprehensive testing and screening of the DRAM chip under different voltage conditions are realized, and potential fault points are effectively identified.

The invention relates to the technical field of spacecraft system-level testing, in particular to a spacecraft multi-user navigation function closed-loop testing system and method, which can realize high-precision comprehensive verification of the navigation function of a spacecraft system and consider the characteristics of multiple tested users, high precision requirement and the like. Aiming at multi-user test requirements of tested spacecrafts, accurate test of a high-dynamic multi-user GNSS simulation source based on a cloud architecture is adopted, multi-spacecraft multi-user simultaneous association test is supported, functional tests such as absolute positioning, relative positioning and trajectory prediction are realized, the system architecture is flexible, the number of user channels is large, and multi-user requirements of complex spacecrafts are supported. According to the method, high-precision comprehensive verification of the navigation function of a spacecraft system can be realized, the characteristics of multiple tested users, high precision requirement and the like are considered, and a high-dynamic multi-user GNSS simulation source spacecraft closed-loop test based on a cloud architecture becomes an effective solution.

The invention relates to a redundant transmission test system, method and equipment based on a ring network Ethernet. The system comprises a tester, a controller to be tested, an Ethernet main line, a first Ethernet branch line and a second Ethernet branch line, the Ethernet main line is provided with a first switch assembly; the first Ethernet branch line is provided with a second switch assembly; the second Ethernet branch line is provided with a third switch assembly; every two adjacent to-be-tested controllers are sequentially connected through an Ethernet main line to form an annular loop. For two adjacent controllers to be tested, one end of the first Ethernet branch line is connected between one controller to be tested and the first switch assembly, the other end of the first Ethernet branch line is connected with one end of the second Ethernet branch line through the tester, and the other end of the second Ethernet branch line is connected between the other controller to be tested and the first switch assembly. Therefore, a ring network Ethernet system-level redundancy transmission test system is constructed, and the system-level test requirements of ring network Ethernet redundancy transmission are met.

The invention discloses a hydraulic turbine unit speed regulator minimum unit simulation modeling method based on hydrodynamics, and belongs to the field of industrial simulation. According to the method, a modeling method is provided, multi-domain minimum unit decomposition is carried out, and a speed regulation system is decoupled into six functional subsystems. State-space equations are established for electric, hydraulic and mechanical equipment of speed regulators such as a proportional valve, a main distributing valve and a main servomotor, and a'control-hydraulic-mechanical 'interface coupling link is constructed. And verifying the model through unit-level and system-level tests. Key physical parameters of the verified unit model are set to be externally adjustable, a centralized parameter database is established, and flexible configuration, efficient multiplexing and dynamic updating of the model are achieved. According to the technical framework, the transparency of a physical mechanism serves as a foundation stone, unification of theoretical preciseness and engineering practicability is formed through a dynamic reconstruction and collaborative verification mechanism, and an autonomous and controllable technical base is constructed for digital design, intelligent regulation and control and service life prediction of major equipment such as hydropower equipment and nuclear power equipment.

The invention discloses a chip testing device, a manipulator chip testing device and a testing method.The chip testing device comprises a testing board, at least one function daughter card and a CPU daughter card, the CPU daughter card is used for sending a test case to a to-be-tested chip for testing and obtaining a testing signal through the function daughter card, and the testing signal is sent to the testing board through the CPU daughter card; and judging a test result of the to-be-tested chip through the test signal, according to the technical scheme, the test board serves as a unified interconnection platform, the CPU daughter card and the function daughter cards work cooperatively, system-level testing of the to-be-tested chip is achieved, the function daughter cards can be conveniently and flexibly increased or decreased according to test requirements, the expansibility and the adaptation capacity of the test system are improved, the signal transmission path can be shortened, and the test efficiency is improved. The stability and the consistency of the test signals are improved, so that the efficiency and the reliability of chip testing are effectively improved.

The application provides a server mainboard-based system-level test adapter and method, and relates to the technical field of chip testing.The device comprises an automated test equipment socket, an adapter plate and a server mainboard.The server mainboard is a chip verification stage mainboard that retains a chip under test socket and a core circuit.The bottom of the adapter plate is provided with first contacts that are consistent with the pin arrangement of the chip under test, so that the bottom of the adapter plate is inserted into and electrically connected to the chip under test socket in the server mainboard.The top of the adapter plate is electrically connected to the automated test equipment socket.The automated test equipment socket is used to install the chip under test and, together with the adapter plate and the server mainboard, forms a mass production system-level test stage mainboard for system-level testing of the chip under test.The application reduces the development and maintenance costs of test hardware and shortens the entire cycle.

The present disclosure relates to a vehicle testing method, device, system, computer device and storage medium. It relates to electric vehicle manufacturing technology and solves the problems of low efficiency, high cost and poor accuracy caused by the testing method highly dependent on manual operation. The method comprises: establishing a test special connection with a vehicle machine of at least one vehicle to be tested; generating a system-level test instruction simulating a control operation and sending it to the vehicle machine to instruct the vehicle machine to perform a test, the system-level test instruction having a higher priority than a user-level instruction. The technical solution provided by the present disclosure is suitable for automobile function testing and realizes automatic testing of electric vehicle functions.

The application discloses a partition-controllable heat simulation device and method for direct cooling plate testing, and belongs to the technical field of energy storage thermal management testing, and solves the problems of existing tests, such as dependence on real batteries, distortion of heat source simulation, uncontrollability of contact thermal resistance, and inability to separate thermal capacity effect. The system comprises a contact type simulation heat source, a fitting pressure applying device and a heating control unit. The contact type simulation heat source comprises a plurality of partition heating modules arranged in a matrix, and can reproduce uniform or non-uniform heat generation under battery pack steady state or transient state. The fitting pressure applying device realizes uniform and quantifiable pressure bonding of the contact type simulation heat source and the whole domain of the direct cooling plate to be tested, and cooperates with a heat-conducting gel to stabilize the contact thermal resistance. The heating control unit realizes independent power regulation and control of each partition heating module. The method is based on the system to complete working condition configuration, heat source fitting, pressure calibration, power regulation and driving, realizes steady state or transient heat simulation, and does not need real battery packs, and can quickly, at low cost and with high fidelity, complete direct cooling plate component-level and system-level testing requirements.

The memory margin test method, system and device and the medium provided by the embodiment of the invention comprise the steps that a main control module generates a test script in response to a received memory time sequence parameter set by a target object and a selected test option; in response to the received test request sent by the system-level test equipment, the main control module sends a test script to the system-level test equipment; the system-level test equipment receives the test script sent by the main control module and executes the test script so as to test a target memory bank set by the system-level test equipment through the test script; and the main control module captures the Bios log in the process of testing the target memory bank by the system-level test equipment, and determines a memory margin test result of the target memory bank set by the system-level test equipment according to the Bios log. Full-process automation of RMT testing is achieved, manual intervention is reduced, and the testing efficiency and the accuracy of memory stability evaluation are improved.

The invention discloses a system-level testing method, electronic equipment and a computer readable storage medium, and the system-level testing method comprises the steps that a central processing unit of a chip is in a full-load operation state, and the central processing unit operates a full-load driving program at a first preset level authority to perform full-load operation, the first preset level is lower than the level of a full-load drive program during a conventional system load test; and determining a test result of full-load operation of the central processing unit. According to the method, the running level of the full-load driving program is reduced, and the execution efficiency of the test case is improved to the greatest extent under the condition of ensuring the effectiveness of the test load of the full-load driving program, so that the total time of the whole production test is reduced, the production efficiency is improved, and the test cost is reduced.

The invention provides a memory test system and test method. The test system is used for selectively operating in a pure hardware test mode or a system-level test mode. Wherein in the pure hardware test mode, starting is carried out from a third-party storage medium independent of the memory so as to load a test system mirror image and a customized kernel; after the customized kernel is started, a test driving module is loaded and a test node is created, and the test driving module is used for shielding a default power management mechanism and / or a retry mechanism of the system and communicating with an upper computer through the test node; the test instruction is issued by the upper computer and is used for testing the memory, and the test state and the test data of the memory are returned. According to the method, the independent test system is loaded from the third-party storage medium independent of the memory instead of starting the Android system from the memory, so that Android system information does not need to be written into the memory, and the problem that the test coverage rate is limited due to the fact that the Android system information occupies part of a storage area in the memory is solved.

A test control process initiates processing of a test case to be used in system level testing of a system unit under test. A query is sent, by the test control process, to a central test manager to determine a history of the test case. The history of the test case is obtained by the test control process based on the query. Processing of the test case continues, based on the history.

The embodiment of the utility model discloses a system-level test circuit of a chip and electronic equipment, and relates to the field of integrated circuit testing. The specific amplifier chip and the analog-to-digital conversion chip are adopted to construct the test circuit, use of an expensive special programmable instrument is avoided, and the purchase and maintenance cost of test equipment is remarkably reduced. The circuit design is simplified, so that the cost of the whole test system is more controllable, and the whole competitiveness of the product is improved. The design of the current and voltage conversion unit and the result measurement unit is relatively simple and clear, and the requirements for professional skills and knowledge reserve of test engineers are reduced. The test process is simplified, the operation steps are reduced, and the test efficiency is improved.