19 results about "System level testing" patented technology

The application relates to the technical field of integrated circuit design and verification, in particular to a service test system for a texture block level, which generates a plurality of accurate controllable screen coordinates through a simulation geometry processing module and a simulation rasterization module and provides the screen coordinates to a texture processing module, so that the texture processing module can independently verify the logic of texture processing based on the generated screen coordinates, the reliability of the texture processing module does not need to be tested through system-level verification for service testing, the test requirement is lowered to the texture block level, thus the workload of system-level testing can be saved, the influence of problems of other modules on the texture processing module testing is avoided, the test difficulty is reduced, and the test efficiency and problem positioning accuracy of the texture block level service test are improved.

The test method, device, equipment and storage medium provided in the application first test each to-be-tested parameter of a preset number of DRAM samples through a system-level test machine and each standard parameter value in a high-temperature environment and a low-temperature environment, to obtain a corresponding first test result, then test each to-be-tested parameter of the DRAM sample with a failed first test result through a test machine and each target parameter value in a normal-temperature environment, to obtain a corresponding second test result. If the second test result is also failed, each to-be-tested parameter of the to-be-tested DRAM is tested through a test machine and each target parameter value in a normal-temperature environment, to realize that the normal-temperature environment replaces the high-temperature environment and the low-temperature environment to perform STL test on the to-be-tested DRAM sample, and test cost and test time are saved.

1. The name of the design product: multi-phase power controller system level test equipment. 2. The use of the design product: the design product is a test equipment for control board, electronic load board and signal detection board, used for simulating multi-phase power controller. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The invention discloses a test system for a remote diagnosis platform. The test system comprises an upper computer, a programmable power supply, a CAN network simulation board card and an entity ECU (Electronic Control Unit), such as a TBOX and a gateway, wherein the upper computer is used for locally running a remote diagnosis platform and a test program; the programmable power supply is used for supplying power to the entity ECU; the CAN network simulation board card is used for simulating a real vehicle network environment; the entity ECU is used as a test object, the TBOX and the gateway are connected through a plurality of diagnosis CAN network segments, and each diagnosis CAN network segment is provided with a plurality of virtual controller nodes. According to the invention, a rack system is established, a core controller related to remote diagnosis is subjected to physical carrying, other controllers are virtualized, and interaction is carried out by establishing a controlled simulation model, so that multi-dimensional system-level testing is carried out on the whole remote diagnosis platform; and full coverage of fault code reading and fault code simulation and reporting scenes of multiple controllers can be realized.

The application discloses an autonomous program control system level test method, and proposes a solution method for the correctness, effectiveness, safety and integrity of satellite active stage operation period satellite-rocket separation program control, autonomous flight program control, synchronous orbit stage operation period machine cutting program control, and emergency program control task verification. Based on satellite 1553B bus data simulation function and automatic test, satellite program control execution process is simulated and forwarded, satellite autonomous instruction sequence during program control execution is analyzed or intercepted, satellite program control process safety risk hidden danger is guaranteed, and effective verification of satellite autonomous program control function and comprehensive interpretation of instruction telemetry are realized.

This application discloses a testing method and laser equipment for a multi-mode master-slave control system, relating to the field of laser testing technology. It obtains structured text representing a hierarchical testing system, including a first text representing board-level characteristic testing rules and a second text representing system-level functional testing rules. Based on the first and second texts, board-level characteristic tests and system-level functional tests are performed on the master control board, slave control board, and beam combiner board, respectively, yielding board-level test results and system-level test results. Based on the board-level and system-level test results, a target text representing a comprehensive test report is generated. This achieves comprehensive testing and verification of the hardware foundation and system functional coordination of each board in the multi-mode master-slave control system, accurately identifying hardware defects and potential collaborative problems on each board. It provides a standardized solution to ensure the overall quality and reliability of the multi-mode master-slave control system, significantly improving the testing efficiency and reliability of the multi-mode master-slave control system.

The application relates to the field of computer storage, and discloses an FPGA-based SSD controller verification method and system, which aims to solve the problems of hardware redundancy, non-systematic verification and poor flexibility of a verification scheme in a high-integration board card environment. Technical solution points: the verification method is divided into three stages, that is, first, a hardware environment is constructed through FPGA integration verification, then, basic functions and performance are tested through data disk verification, and finally, system-level testing and version solidification are completed through system disk verification; the verification system comprises a host computer and an integrated board card, and an FPGA module integrates an SSD controller and network interface function logic. The application does not require additional hardware, realizes low-cost and systematic comprehensive verification, and is suitable for function and performance verification of an SSD controller in a high-integration board card environment.

The application provides a chip system-level test platform and a chip system-level test method, which comprises test board cards corresponding to each chip to be tested, a plurality of shared test modules and a field programmable gate array. The test board card comprises a plurality of unique test modules corresponding to the chip to be tested, each shared test module is connected with each test board card for shared use of each test board card. The field programmable gate array is connected with each shared test module and the chip to be tested, and is used for shared multiplexing control of each shared test module according to the requirement of each chip to be tested for each shared test module. In the scheme, each test board card is provided with a plurality of shared test modules in a shared manner, and is managed by the field programmable gate array, so that the size of the test board card is greatly reduced, the hardware resources are shared, more parallel tests of the test board cards can be realized on the limited test platform, and the test cost and the hardware resource overhead are greatly reduced.

The invention discloses a voltage-regulated DRAM (Dynamic Random Access Memory) system-level test system and a screening method thereof. The system comprises a test mainboard, an external programmable current source module, an upper computer and a control panel. The test mainboard is integrated with a DRAM (Dynamic Random Access Memory) chip and a SoC (System on Chip), wherein the power supply input end of the DRAM chip and the PMIC are in an electrical open circuit state. The external current source module is independent of the SoC and the PMIC and provides multiple paths of independently adjusted power supply voltages for the DRAM chip. The upper computer is used for configuring a voltage change curve and triggering a test process, and the control panel is responsible for receiving an instruction of the upper computer and controlling the current source module to output a corresponding voltage value through a serial bus. Based on the system, the invention provides a screening method, different voltage conditions are applied to the DRAM chip, system-level testing is executed, and finally grading screening or reliability grade evaluation of the DRAM device is achieved. According to the invention, comprehensive testing and screening of the DRAM chip under different voltage conditions are realized, and potential fault points are effectively identified.

The invention discloses a hydraulic turbine unit speed regulator minimum unit simulation modeling method based on hydrodynamics, and belongs to the field of industrial simulation. According to the method, a modeling method is provided, multi-domain minimum unit decomposition is carried out, and a speed regulation system is decoupled into six functional subsystems. State-space equations are established for electric, hydraulic and mechanical equipment of speed regulators such as a proportional valve, a main distributing valve and a main servomotor, and a'control-hydraulic-mechanical 'interface coupling link is constructed. And verifying the model through unit-level and system-level tests. Key physical parameters of the verified unit model are set to be externally adjustable, a centralized parameter database is established, and flexible configuration, efficient multiplexing and dynamic updating of the model are achieved. According to the technical framework, the transparency of a physical mechanism serves as a foundation stone, unification of theoretical preciseness and engineering practicability is formed through a dynamic reconstruction and collaborative verification mechanism, and an autonomous and controllable technical base is constructed for digital design, intelligent regulation and control and service life prediction of major equipment such as hydropower equipment and nuclear power equipment.

The invention discloses a chip testing device, a manipulator chip testing device and a testing method.The chip testing device comprises a testing board, at least one function daughter card and a CPU daughter card, the CPU daughter card is used for sending a test case to a to-be-tested chip for testing and obtaining a testing signal through the function daughter card, and the testing signal is sent to the testing board through the CPU daughter card; and judging a test result of the to-be-tested chip through the test signal, according to the technical scheme, the test board serves as a unified interconnection platform, the CPU daughter card and the function daughter cards work cooperatively, system-level testing of the to-be-tested chip is achieved, the function daughter cards can be conveniently and flexibly increased or decreased according to test requirements, the expansibility and the adaptation capacity of the test system are improved, the signal transmission path can be shortened, and the test efficiency is improved. The stability and the consistency of the test signals are improved, so that the efficiency and the reliability of chip testing are effectively improved.

The application provides a server mainboard-based system-level test adapter and method, and relates to the technical field of chip testing.The device comprises an automated test equipment socket, an adapter plate and a server mainboard.The server mainboard is a chip verification stage mainboard that retains a chip under test socket and a core circuit.The bottom of the adapter plate is provided with first contacts that are consistent with the pin arrangement of the chip under test, so that the bottom of the adapter plate is inserted into and electrically connected to the chip under test socket in the server mainboard.The top of the adapter plate is electrically connected to the automated test equipment socket.The automated test equipment socket is used to install the chip under test and, together with the adapter plate and the server mainboard, forms a mass production system-level test stage mainboard for system-level testing of the chip under test.The application reduces the development and maintenance costs of test hardware and shortens the entire cycle.

The present disclosure relates to a vehicle testing method, device, system, computer device and storage medium. It relates to electric vehicle manufacturing technology and solves the problems of low efficiency, high cost and poor accuracy caused by the testing method highly dependent on manual operation. The method comprises: establishing a test special connection with a vehicle machine of at least one vehicle to be tested; generating a system-level test instruction simulating a control operation and sending it to the vehicle machine to instruct the vehicle machine to perform a test, the system-level test instruction having a higher priority than a user-level instruction. The technical solution provided by the present disclosure is suitable for automobile function testing and realizes automatic testing of electric vehicle functions.

The application discloses a partition-controllable heat simulation device and method for direct cooling plate testing, and belongs to the technical field of energy storage thermal management testing, and solves the problems of existing tests, such as dependence on real batteries, distortion of heat source simulation, uncontrollability of contact thermal resistance, and inability to separate thermal capacity effect. The system comprises a contact type simulation heat source, a fitting pressure applying device and a heating control unit. The contact type simulation heat source comprises a plurality of partition heating modules arranged in a matrix, and can reproduce uniform or non-uniform heat generation under battery pack steady state or transient state. The fitting pressure applying device realizes uniform and quantifiable pressure bonding of the contact type simulation heat source and the whole domain of the direct cooling plate to be tested, and cooperates with a heat-conducting gel to stabilize the contact thermal resistance. The heating control unit realizes independent power regulation and control of each partition heating module. The method is based on the system to complete working condition configuration, heat source fitting, pressure calibration, power regulation and driving, realizes steady state or transient heat simulation, and does not need real battery packs, and can quickly, at low cost and with high fidelity, complete direct cooling plate component-level and system-level testing requirements.

The invention provides a memory test system and test method. The test system is used for selectively operating in a pure hardware test mode or a system-level test mode. Wherein in the pure hardware test mode, starting is carried out from a third-party storage medium independent of the memory so as to load a test system mirror image and a customized kernel; after the customized kernel is started, a test driving module is loaded and a test node is created, and the test driving module is used for shielding a default power management mechanism and / or a retry mechanism of the system and communicating with an upper computer through the test node; the test instruction is issued by the upper computer and is used for testing the memory, and the test state and the test data of the memory are returned. According to the method, the independent test system is loaded from the third-party storage medium independent of the memory instead of starting the Android system from the memory, so that Android system information does not need to be written into the memory, and the problem that the test coverage rate is limited due to the fact that the Android system information occupies part of a storage area in the memory is solved.

A test control process initiates processing of a test case to be used in system level testing of a system unit under test. A query is sent, by the test control process, to a central test manager to determine a history of the test case. The history of the test case is obtained by the test control process based on the query. Processing of the test case continues, based on the history.

The embodiment of the utility model discloses a system-level test circuit of a chip and electronic equipment, and relates to the field of integrated circuit testing. The specific amplifier chip and the analog-to-digital conversion chip are adopted to construct the test circuit, use of an expensive special programmable instrument is avoided, and the purchase and maintenance cost of test equipment is remarkably reduced. The circuit design is simplified, so that the cost of the whole test system is more controllable, and the whole competitiveness of the product is improved. The design of the current and voltage conversion unit and the result measurement unit is relatively simple and clear, and the requirements for professional skills and knowledge reserve of test engineers are reduced. The test process is simplified, the operation steps are reduced, and the test efficiency is improved.

The invention relates to a chip latch-up effect testing method and device, equipment and a storage medium, and relates to the technical field of chip testing. When the tested chip is in the system-level test stage, the target output voltage of the chip power supply is adjusted to the maximum stress voltage of the tested chip, and the target output voltage is the voltage output by the chip power supply to the tested chip; obtaining an input current of a chip power supply, wherein the input current is in positive correlation with a working current of the tested chip under the action of the maximum stress voltage; based on the magnitude relationship between the input current and the target threshold current, the latch-up effect test result of the tested chip is determined, the target threshold current is the lowest input current of the chip power supply corresponding to the latch-up effect of the tested chip, and latch-up effect test can be performed on the chip in the system-level test stage of the chip. The latch-up effect test of the chip in a real application scene is realized, the accuracy and efficiency of the chip latch-up effect test are improved, and the test cost is reduced.

The application discloses a chip SKU distribution regulation method, equipment and a storage medium, relates to the technical field of integrated circuit testing, and the chip SKU distribution regulation method comprises the following steps: when performing system-level testing on a chip at a target SKU gear, if the number of passed chips is not less than a SKU number threshold or the chip fails the test, adjusting the target SKU gear based on a chip parameter file, returning to the steps of judging whether the number of chips is less than the SKU number threshold and whether the chip passes, until a chip test result is obtained, and the shipment SKU gear of the chip is determined. The application can adjust the SKU gear and limit the number of SKUs corresponding to each gear during testing, realize the adjustment of the shipment chip SKU proportion distribution, and improve the yield and flexibility of chip shipment. When the chip fails the test, the chip is not directly discarded, but the SKU gear is adjusted for the next round of testing, thereby improving the yield of shipment.