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Sparse matrix storage and calculation system and method

A sparse matrix and sub-matrix technology, applied in the field of sparse matrix storage and calculation systems, can solve problems such as low calculation efficiency, calculation errors, and large storage space, and achieve the effect of taking into account storage efficiency, improving compression efficiency, and improving storage efficiency

Active Publication Date: 2021-10-15
HUAZHONG UNIV OF SCI & TECH
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  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the defects of the prior art, the purpose of the present invention is to provide a sparse matrix storage and calculation system and method, aiming at solving the problem that the existing sparse matrix storage and matrix-vector multiplication cannot remove 0 elements, and 0 elements not only waste storage space, and will introduce calculation errors, increase unnecessary energy consumption and calculation delay, therefore, there are problems of large storage space and low calculation efficiency in the process of sparse matrix storage and matrix-vector multiplication

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  • Sparse matrix storage and calculation system and method

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Embodiment 1

[0056] Such as figure 2 As shown, when the sparse matrix to be processed is an n×n diagonal matrix 6, first determine the block parameters according to the actual needs, assuming that the calculation is divided into two blocks, and call the block algorithm 7 of the diagonal matrix, which is divided into upper and lower two a sub-matrix;

[0057] Eliminate all zero columns and save columns containing non-zero elements, such as the first sub-matrix 7-1 and the second sub-matrix 7-2;

[0058] The first sub-matrix 7-1 and the second sub-matrix 7-2 are stored in the second storage array 3-3, and corresponding indexes are set up and stored in the first storage array; the index situation is specifically: the first sub-matrix in this embodiment The columns of the matrix 7-1 are 1~n / 2+1 columns; the columns of the second sub-matrix 7-2 are n / 2~n columns, and the column information is stored in the second storage array 3-3;

[0059] When the multiplication operation of the sparse mat...

Embodiment 2

[0067] Such as image 3 As shown, when the sparse matrix to be processed is an n×n triangular matrix 11, first determine the block parameters according to the actual needs, assuming that the calculation is divided into two blocks, and call the block algorithm 12 of the diagonal matrix, which is divided into upper and lower sub matrix;

[0068] Eliminate all zero columns and save columns containing non-zero elements, such as the first sub-matrix 12-1 and the second sub-matrix 12-2;

[0069] The first sub-matrix 12-1 and the second sub-matrix 12-2 are stored in the second storage array 3-3, and corresponding indexes are set up and stored in the first storage array; the index situation is specifically: the first sub-matrix in this embodiment The columns of the matrix 12-1 are 1-n / 2 columns; the columns of the second sub-matrix 12-2 are 1-n columns, and the column information is stored in the second storage array 3-3;

[0070] When the multiplication operation of the sparse matr...

Embodiment 3

[0077] Such as Figure 4 As shown, when the processed matrix is ​​an n×n random sparse matrix 15, the traditional indented storage format is adopted first, and all the non-zero elements of each row are concentrated at the head of the row, as shown in 15-1;

[0078] Build an index table 16 and store it in the storage area of ​​the first storage array;

[0079] When it is necessary to perform matrix-vector multiplication, the vector is sent from the main processor to the second peripheral circuit, and the second peripheral circuit converts the vector into a voltage signal;

[0080] Load the index table from the storage area to the on-chip cache 4, because the elements of each row are not aligned in columns, so in this case, calculations need to be performed row by row. The header of the index table is the row number, and the column number of the row element Stored as a linked list element, so when performing calculations, load a linked list of the index table in turn, convert i...

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Abstract

The invention provides a sparse matrix storage and calculation system and method, and belongs to the field of microelectronic devices. The system comprises a first storage array which is used for storing a coordinate index table of non-zero elements of a sparse matrix; the second storage array is used for storing elements of the sparse matrix and also serves as an in-situ calculation kernel of sparse matrix multiplication; the block storage scheduling unit is used for partitioning the sparse matrix into a plurality of sub-matrixes and storing the sub-matrixes into a second storage array according to different compression formats, and establishing an index table corresponding to the sparse matrix; and the second peripheral circuit is used for converting the vector into a voltage signal and applying the voltage signal to a bit line or a word line corresponding to a sub-matrix of the sparse matrix to complete multiplication of the sparse matrix and the vector.

Description

technical field [0001] The invention belongs to the field of microelectronic devices, and more specifically relates to a sparse matrix storage and calculation system and method. Background technique [0002] Sparse matrix is ​​a common matrix in scientific and engineering calculations, but because its 0 elements account for most of the entire matrix, and 0 elements are meaningless for matrix calculations, therefore, the storage and calculation efficiency of sparse matrices Low. [0003] The storage of sparse matrices and matrix-vector multiplication have always been a major challenge in the field of computers and microelectronics, especially in memory computing. Due to the natural in-situ computing and high parallelism of memory computing technology, the location of matrix element storage There are very strict alignment requirements, so in the case of complete parallelism, if the sparse matrix is ​​not mathematically transformed, it is impossible to remove the 0 elements, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C8/06G11C8/08G11C8/10G11C8/16
CPCG11C8/10G11C8/16G11C8/08G11C8/06
Inventor 李祎杨岭缪向水
Owner HUAZHONG UNIV OF SCI & TECH
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