Roller Arbitration Method and Circuit for On-Chip Data Exchange

A technology of data exchange and arbitration method, which is applied in the direction of electrical digital data processing, digital computer components, architecture with a single central processing unit, etc., and can solve problems such as difficulty in realizing high-speed circuits, fairness and complexity, and difficult iterative arbitration , to achieve the effect of easy high-speed circuit, short arbitration time and simple judgment logic

A technology of data exchange and arbitration method, which is applied in the direction of electrical digital data processing, digital computer components, architecture with a single central processing unit, etc., and can solve problems such as difficulty in realizing high-speed circuits, fairness and complexity, and difficult iterative arbitration , to achieve the effect of easy high-speed circuit, short arbitration time and simple judgment logic

CN113568849BActive Publication Date: 2022-04-22HEXAFLAKE (NANJING) INFORMATION TECH CO LTD

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  • Roller Arbitration Method and Circuit for On-Chip Data Exchange
  • Roller Arbitration Method and Circuit for On-Chip Data Exchange
  • Roller Arbitration Method and Circuit for On-Chip Data Exchange

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0049] The present invention will be further described below in conjunction with embodiment, but protection scope of the present invention is not limited to this:

[0050] figure 1 An NxN cross network routing structure is given: each intersection of I0, I1, ..., IN-1 and O0, O1, ..., ON-1 is a routing path, also called a transmission pair. Each intersection is a VOQij request path, the first number of the VOQ subscript indicates the input port number, and the second number indicates the output port number. Each input port Ii can only have one routing node selected in one cycle, and each output port can only have one routing node selected in one cycle. There are at most N paths selected in one cycle.

[0051] In order to ensure that each input port realizes fair arbitration, each input port obtains the data transmission volume as equal as possible, and each virtual output queue VOQ of each input port obtains the data transmission volume as equal as possible, the invention di...

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Abstract

The invention discloses a roller arbitration method for on-chip data exchange, which is based on an NxN crossover network with N input ports and N output ports, comprising the following steps: S1, determining a priority arbitration arrangement; S2, judging whether each expected transmission pair in the arrangement has transmission demand, if yes, it is determined as the actual transmission pair, and the determined actual transmission pair immediately transmits data; otherwise, it is determined as a non-transmission pair; S3, perform sequential row / column or column / row arbitration, and select the switching point with high priority as the actual Transmission pair; S4, after the polling in step S3 is completed, the priority arbitration arrangement is scrolled to obtain a new arbitration arrangement; S5, S2-S4 is performed in a loop. This method can improve the efficiency and speed of on-chip data exchange, and is especially suitable for artificial intelligence and big data processing chips, especially chips with SIMT architecture. Such methods pertain to chip design, network-on-chip, system-on-chip, and computer architecture.

Description

technical field [0001] The invention relates to the fields of chip design, on-chip network, on-chip system, and computer architecture, in particular to a wheel scheduling method and circuit realization of an on-chip data exchange network. This method can improve the efficiency and speed of on-chip data exchange, and is especially suitable for artificial intelligence and big data processing chips, especially chips with SIMT architecture. Background technique [0002] Machine learning, scientific computing and graphics rendering require huge computing power, which is generally provided by large chips (such as GPU, TPU, APU, etc.) to achieve highly complex machine learning tasks and graphics processing tasks. Using machine learning to do recognition requires a huge Deep Learning network and massive image data, and the training process is very time-consuming; in a 3D application or game scene, if Recursive Ray-Tracing is used for rendering, and the scene If it is complex, it ne...

Claims

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Application Information

Patent Timeline
22 Apr 2022
Publication
CN113568849B
IPC
G06F13/16; G06F13/18; G06F15/163; G06F15/78
CPC
G06F13/1642; G06F13/18; G06F15/163; G06F15/7807
Inventors
王东辉; 赵鹏