Semiconductor packaging device and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises the components of rewiring layers, a reinforcing layer, a first electronic element and a second electronic element; the rewiring layers comprise an upper rewiring layer and a lower rewiring layer; the reinforcing layer is arranged between the upper rewiring layer and the lower rewiring layer, and the reinforcing layer is provided with a joint interface; and the first electronic element and the second electronic element are arranged on the rewiring layers. According to the semiconductor packaging device and manufacturing method thereof provided by the technical schemes, the reinforcing layer rigidly supports the rewiring layers, and the reinforcing layer can provide pulling force for the rewiring layers to reduce warping of the rewiring layers, so that the risk that a conductive circuit is broken due to warping of the rewiring layers is reduced.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device and a manufacturing method thereof. Background technique [0002] In the current Fan Out Chip on Substrate (FOCOS) structure, since the thermal expansion coefficient of the dielectric material in the redistribution layer is significantly greater than the thermal expansion coefficient of the metal material of the conductive line, as the number of redistribution layers increases, It is easy to increase the warpage of the entire redistribution layer due to the difference in thermal expansion coefficient of the material, because the conductive lines of the redistribution layer cannot bear the pull of warping, and then produce such as figure 1 The problem of broken conductive lines shown in the middle dotted line. Contents of the invention [0003] In a first aspect, the present disclosure provides a semiconductor packaging ...

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Problems solved by technology

[0002] In the current Fan Out Chip on Substrate (FOCOS) structure, since the thermal expansion coefficient of the dielectric material in the redistribution layer is significantly greater than the thermal expansion coefficient of the metal material of the conductive line, as the number of redistribution layers increases, It is easy to increase the warpage of the entire redistribution layer due to the difference in thermal expansion coefficient of the material, because the conductive lines of the redistribution layer cannot bear the pull of warping, and then produce such as figure 1 The problem of broken conductive lines shown in the dotted line in the middle

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