Storage array circuit, storage array layout and verification method

Abstract

The embodiment of the invention provides a storage array circuit, a storage array layout and a verification method. The storage array circuit comprises M word lines; M word line breaking nodes, wherein each word line breaking node is used for separating a corresponding word line into a first word line pin and a second word line pin; N bit lines; N bit line breaking nodes, wherein each bit line breaking node is used for separating a corresponding bit line into a first bit line pin and a second bit line pin, wherein the M and the N are positive even numbers. According to the embodiment of the invention, the layout of the word line layer and the bit line layer can be verified.

Description

Technical field [0001] Embodiments of the present application relate to semiconductor technology, and in particular, to a storage array circuit, a storage array layout, and a verification method. Background technique [0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device that is commonly used in the computer, composed of many duplicated storage units. Each memory cell typically includes a capacitor and a transistor, the gate of the transistor is connected to the word line, and the drain is connected to the bit line. The source is connected to the capacitor, and the voltage signal on the word line can control the opening or closing of the transistor, and then passes through the bit line Read the data information stored in the capacitor or write data information to the capacitor by bit line. [0003] The memory has a plurality of word lines and multiple bit lines, a layout of the word line and bit line meets the requirements, which determines the performance ...

AI Technical Summary

Problems solved by technology

However, the current methods for verifying whether the layout of word lines and bit lines meet the requirements cannot effectively perform layout versus schematic (LVS) consistency verification for word lines and bit lines to verify the layout of word lines and bit lines. The layout meets the requirements

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